DR. SCOTT D'WAYNE SMITH, MD
Medical Practice at Pinnacle Hills Pkwy, Rogers, AR
License number
Arkansas E3426
Category
Medical Practice
Type
Obstetrics & Gynecology
Address
Address
3333 Pinnacle Hills Pkwy SUITE 300, Rogers, AR 72758
Phone
(479) 464-7171
(479) 464-0030 (Fax)
(479) 464-0030 (Fax)
Professional information
Dr. Scott D Smith, Rogers AR - MD (Doctor of Medicine)
Specialties:
Obstetrics & Gynecology
Address:
Pinnacle Women's Health Care
3333 Pinnacle Hills Pkwy STE 300, Rogers 72758
(479) 464-7171 (Phone)
3333 Pinnacle Hills Pkwy STE 300, Rogers 72758
(479) 464-7171 (Phone)
Certifications:
Obstetrics & Gynecology, 2004
Awards:
Healthgrades Honor Roll
Languages:
English, Spanish
Education:
Medical School
Texas Tech University Health Sciences Center School Of Medicine
Graduated: 1994
Nw Tx Hospital
Graduated: 1995
Tx Tech/Nw Tx Hospital
Graduated: 1998
Texas Tech University Health Sciences Center School Of Medicine
Graduated: 1994
Nw Tx Hospital
Graduated: 1995
Tx Tech/Nw Tx Hospital
Graduated: 1998
Scott D'Wayne Smith, Rogers AR
Specialties:
Obstetrics & Gynecology, Orthopaedic Surgery
Work:
Pinnacle Womens Healthcare
5511 Walsh Ln, Rogers, AR 72758
5511 Walsh Ln, Rogers, AR 72758
Education:
Texas Tech University(1994)
Ultra-Low Power Multi-Threshold Asynchronous Circuit Design
US Patent:
7977972, Jul 12, 2011
Filed:
Apr 30, 2010
Appl. No.:
12/771886
Inventors:
Jia Di - Fayetteville AR, US
Scott Christopher Smith - Rogers AR, US
Scott Christopher Smith - Rogers AR, US
Assignee:
The Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H03K 19/173
US Classification:
326 46, 326 93, 326 21
Abstract:
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
Ultra-Low Power Multi-Threshold Asynchronous Circuit Design
US Patent:
8207758, Jun 26, 2012
Filed:
Jul 1, 2011
Appl. No.:
13/175168
Inventors:
Jia Di - Fayetteville AR, US
Scott Christopher Smith - Rogers AR, US
Scott Christopher Smith - Rogers AR, US
Assignee:
The Board of Trustees of the University of Arkansas - Little Rock AR
International Classification:
H03K 19/20
US Classification:
326120, 326 93, 326 27, 326121
Abstract:
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
Ultra-Low Power Multi-Threshold Asynchronous Circuit Design
US Patent:
2012029, Nov 22, 2012
Filed:
May 24, 2012
Appl. No.:
13/479706
Inventors:
Jia Di - Fayetteville AR, US
Scott Christopher Smith - Rogers AR, US
Scott Christopher Smith - Rogers AR, US
Assignee:
THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS - Little Rock AR
International Classification:
H03K 19/003, H05K 13/00
US Classification:
326 21, 29825
Abstract:
A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.
Multi-Threshold Sleep Convention Logic Without Nsleep
US Patent:
2013018, Jul 18, 2013
Filed:
Jan 11, 2013
Appl. No.:
13/739778
Inventors:
Scott Christopher Smith - Rogers AR, US
Jia Di - Fayetteville AR, US
Jia Di - Fayetteville AR, US
Assignee:
THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSA - Little Rock AR
International Classification:
H03K 19/173
US Classification:
326 46
Abstract:
A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.