Scott Campbell
Pharmacy at 4 St, Longmont, CO
License number
Colorado 76344
Issued Date
Dec 4, 2001
Renew Date
Oct 1, 2014
Expiration Date
Sep 30, 2017
Type
Residential Wireman
Address
Address
2
1125 4Th St, Longmont, CO 80513
Longmont, CO
Longmont, CO
Personal information
See more information about Scott Campbell at radaris.comName
Address
Phone
4550 W 90Th Ave, Westminster, CO 80031
70 W 6Th Ave #210, Denver, CO 80204
1595 Fillmore St, Denver, CO 80206
800 Pennsylvania St, Denver, CO 80203
Professional information
Staff Product Applications Engineer At Xilinx
Position:
Staff Product Applications Engineer at Xilinx
Location:
Greater Denver Area
Industry:
Semiconductors
Work:
Xilinx
- Longmont, Co since Jul 1999
-
Staff Product Applications Engineer
Western Digital
Jul 2010 - Mar 2012
-
Senior Principal Engineer
Xilinx
Jul 1999 - Jul 2010
-
Staff Technical Marketing Engineer
Education:
University of California, Davis 1997 - 1999
American River Community College 1994 - 1997
American River Community College 1994 - 1997
Digital Logic Circuit For Adding Three Binary Words And Method Of Implementing Same
US Patent:
7653677, Jan 26, 2010
Filed:
Jan 26, 2005
Appl. No.:
11/044744
Inventors:
Scott J. Campbell - Frederick CO, US
Brian D. Philofsky - Longmont CO, US
Lyman D. Lewis - Hudson NH, US
Brian D. Philofsky - Longmont CO, US
Lyman D. Lewis - Hudson NH, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 7/50
US Classification:
708709
Abstract:
A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a carry generation portion and a sum generation portion. The carry generation portion is configured to generate a first carry signal from a second set of three input signals. The sum generation portion is configured to generate a second sum signal from the first sum signal and the first carry signal. The carry chain logic is configured to process the first sum signal, the second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal.
Apparatus And Method For Automated Determination Of Timing Constraints
US Patent:
8091056, Jan 3, 2012
Filed:
May 29, 2009
Appl. No.:
12/474964
Inventors:
Scott J. Campbell - Frederick CO, US
Mona D. Rideout - Fort Collins CO, US
Paul J. Glairon - Longmont CO, US
Mona D. Rideout - Fort Collins CO, US
Paul J. Glairon - Longmont CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716113, 716106, 716108, 716102
Abstract:
A method and apparatus is provided for the automatic creation of timing constraints that are based upon input interface timing parameters entered through a graphical user interface that is associated with the one or more input interfaces. Ideal timing constraints are created from the input interface timing parameters for the one or more input interfaces, thereby enabling the analysis of the input interface(s) without requiring explicit constraints to be defined by the designer of the input interface(s). Timing constraints may, therefore, be automatically generated by the designer without the need for the designer to possess any detailed knowledge of the associated constraint language parameters. Once created, the automatically generated timing constraints are graphically displayed to the designer for verification and/or modification. The automated process removes any potential for improperly defining the input constraint language parameters associated with the input interface(s).
Integrated Circuit And Method Of Reading Data From A Memory Device
US Patent:
6925014, Aug 2, 2005
Filed:
Jun 2, 2004
Appl. No.:
10/860238
Inventors:
Thomas E. Fischaber - Golden CO, US
Scott J. Campbell - Frederick CO, US
Scott J. Campbell - Frederick CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C007/00
US Classification:
36518901, 36518905
Abstract:
A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOS. A blockRAM based zero-cycle latency read FIFO is also described.
Parallel Keystream Decoder
US Patent:
7092906, Aug 15, 2006
Filed:
Mar 12, 2004
Appl. No.:
10/799183
Inventors:
Scott J. Campbell - Frederick CO, US
Thomas E. Fischaber - Golden CO, US
Thomas E. Fischaber - Golden CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/00
US Classification:
705 50, 705 51, 705 57
Abstract:
Methods and circuitry are disclosed for decoding a keystream. A set of test bits is generated, and a set of attempted keystream bits are generated from differences between the test bits and an input set of cipher bits. A set of current keystream bits are generated from a current seed using a parallel feedback shift register, and the attempted keystream bits are compared to the current keystream bits. In response to attempted keystream bits being equal to the current keystream bits, the current keystream bits are fed back as a new current seed. In response to attempted keystream bits being not equal to the current keystream bits, the attempted keystream bits are fed back as the new current seed.
Integrated Circuit And Method Of Outputting Data From A Fifo
US Patent:
6848042, Jan 25, 2005
Filed:
Mar 28, 2003
Appl. No.:
10/402742
Inventors:
Scott J. Campbell - Frederick CO, US
Thomas E. Fischaber - Golden CO, US
Jeremy B. Goolsby - Longmont CO, US
Thomas E. Fischaber - Golden CO, US
Jeremy B. Goolsby - Longmont CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1500, G06F 1200
US Classification:
712 35, 711 5, 711119
Abstract:
A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.
Timing Annotation Accuracy Through The Use Of Static Timing Analysis Tools
US Patent:
7451417, Nov 11, 2008
Filed:
May 12, 2006
Appl. No.:
11/433127
Inventors:
Scott J. Campbell - Longmont CO, US
Mario Escobar - Boulder CO, US
Jaime D. Lujan - Louisville CO, US
Brian D. Philofsky - Longmont CO, US
Mario Escobar - Boulder CO, US
Jaime D. Lujan - Louisville CO, US
Brian D. Philofsky - Longmont CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 4, 716 5
Abstract:
A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.
Integrated Circuit And Method Of Reading Data From A Memory Device
US Patent:
6847558, Jan 25, 2005
Filed:
Mar 28, 2003
Appl. No.:
10/402743
Inventors:
Thomas E. Fischaber - Golden CO, US
Scott J. Campbell - Frederick CO, US
Scott J. Campbell - Frederick CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 700
US Classification:
36518901, 36518905, 36518912
Abstract:
A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOs. A blockRAM based zero-cycle latency read FIFO is also described.
Annotating Timing Information For A Circuit Design For Increased Timing Accuracy
US Patent:
7421675, Sep 2, 2008
Filed:
Jan 17, 2006
Appl. No.:
11/333863
Inventors:
Scott J. Campbell - Frederick CO, US
Mario Escobar - Boulder CO, US
Jaime D. Lujan - Louisville CO, US
Brian D. Philofsky - Longmont CO, US
Mario Escobar - Boulder CO, US
Jaime D. Lujan - Louisville CO, US
Brian D. Philofsky - Longmont CO, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G06F 9/45, G06F 17/50
US Classification:
716 6, 716 4, 716 5, 703 19
Abstract:
A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.