SCOTT ADAM DZIAK
Pilots at Cinquefoil Ln, Fort Collins, CO

License number
Colorado A5067592
Issued Date
Dec 2012
Expiration Date
Dec 2013
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
5315 Cinquefoil Ln, Fort Collins, CO 80528

Professional information

Scott Dziak Photo 1

Principal Engineer At Lsi

Position:
Principal Engineer at LSI Corporation
Location:
Fort Collins, Colorado Area
Industry:
Semiconductors
Work:
LSI Corporation since Sep 2003 - Principal Engineer Vitesse Semiconductor May 2000 - Jul 2003 - Principal Engineer SiTera Sep 1997 - May 2000 - Senior Design Engineer Hewlett-Packard Jul 1994 - Aug 1997 - Member of Technical Staff
Education:
University of Wisconsin-Madison 1992 - 1994
MSEE, VLSI Design, Computer Architecture, DSP
University of Wisconsin-Madison 1988 - 1992
BSEE, Electrical Engineering, Computer Engineering


Scott Dziak Photo 2

Systems And Methods For Medium Proximity Detection In A Read Channel

US Patent:
2013014, Jun 13, 2013
Filed:
Nov 30, 2012
Appl. No.:
13/690435
Inventors:
LSI Corporation - Milpitas CA, US
Erich F. Haratsch - Bethlehem PA, US
Jason S. Goldberg - St. Paul MN, US
Kurt J. Worrell - Berthoud CO, US
Scott M. Dziak - Fort Collins CO, US
Jeffrey P. Grundvig - Loveland CO, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G11B 27/36
US Classification:
360 55
Abstract:
A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the aggregated value to an aggregate threshold to yield an aggregate output; and generating a contact event output if one or more of a first group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value and a predefined minimum number of a second group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value.


Scott Dziak Photo 3

Systems And Methods For Low Latency Media Defect Detection

US Patent:
8139457, Mar 20, 2012
Filed:
Sep 23, 2008
Appl. No.:
12/236148
Inventors:
Yang Cao - Longmont CO, US
Scott M. Dziak - Fort Collins CO, US
Nayak Ratnakar Aravind - Lancaster PA, US
Richard Rauschmayer - Longmont CO, US
Weijun Tan - Longmont CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11B 20/18
US Classification:
369 5316
Abstract:
Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.


Scott Dziak Photo 4

Systems And Methods For Reduced Latency Loop Correction

US Patent:
8610608, Dec 17, 2013
Filed:
Mar 8, 2012
Appl. No.:
13/415430
Inventors:
Nayak Ratnakar Aravind - Allentown PA, US
Scott M. Dziak - Fort Collins CO, US
Haitao Xia - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
H03M 1/06
US Classification:
341118, 360 51, 360134, 360 46, 360 53
Abstract:
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes: a data detector circuit, a low latency detection circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output, and to provide a loop error as a difference between the detected output and the first signal. The low latency detection circuit operable to process a second signal derived from the data input to yield a fast detector output, and to provide a generated error as a difference between the fast detector output and the second signal. The error calculation circuit is operable to calculate an error value based at least in part on the generated error and the loop error.


Scott Dziak Photo 5

Systems And Methods For Memory Efficient Signal And Noise Estimation

US Patent:
2010008, Apr 8, 2010
Filed:
Oct 8, 2008
Appl. No.:
12/247378
Inventors:
George Mathew - San Jose CA, US
Yuan Xing Lee - San Jose CA, US
Hongwei Song - Longmont CO, US
David L. Parker - Firestone CO, US
Scott M. Dziak - Fort Collins CO, US
International Classification:
G06F 7/38, G06F 7/50, G06F 7/52
US Classification:
708445, 708670, 708620
Abstract:
Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a N×Ndata pattern. The N×Ndata pattern includes Nbits repeated Ntimes. Both Nand Nare each greater than one. The methods further include performing an initial read of the N×Ndata pattern, which is stored to a first register. Nsubsequent reads of the N×Ndata pattern are each processed by: performing a subsequent read of the N×Ndata pattern, and performing a difference calculation using the initial read of the N×Ndata pattern and the subsequent read of the N×Ndata pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored N×Ndata pattern and the stored difference vector, an electronics noise power is calculated.


Scott Dziak Photo 6

Systems And Methods For Low Latency Media Defect Detection

US Patent:
2013020, Aug 8, 2013
Filed:
Feb 8, 2012
Appl. No.:
13/368599
Inventors:
Yang Cao - Longmont CO, US
Scott M. Dziak - Fort Collins CO, US
Nayak Ratnakar Aravind - Lancaster PA, US
Richard Rauschmayer - Longmont CO, US
Weijun Tan - Longmont CO, US
International Classification:
G06F 11/07
US Classification:
714799, 714E11024
Abstract:
Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value.


Scott Dziak Photo 7

Zero Gain Start Bias Estimation

US Patent:
2014003, Feb 6, 2014
Filed:
Aug 2, 2012
Appl. No.:
13/564763
Inventors:
Haotian Zhang - Longmont CO, US
Scott Michael Dziak - Fort Collins CO, US
Haitao Xia - San Jose CA, US
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G11B 5/03
US Classification:
360 66, G9B 5031
Abstract:
A method and system for estimating a zero gain start (ZGS) bias in a read channel is disclosed. The method may include: receiving preamble samples within a fixed-length window selected for ZGS calculation; calculating an energy associated with a 2T frequency in the preamble samples; calculating an energy associated with non-2T frequencies in the preamble samples; and calculating the ZGS bias based on the energy associated with the 2T frequency in the preamble samples and the energy associated with non-2T frequencies in the preamble samples.


Scott Dziak Photo 8

Systems And Methods For Defective Media Region Identification

US Patent:
7952824, May 31, 2011
Filed:
Mar 6, 2009
Appl. No.:
12/399679
Inventors:
Scott M. Dziak - Fort Collins CO, US
Nayak Ratnakar Aravind - Lancaster PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11B 27/36
US Classification:
360 31
Abstract:
Various embodiments of the present invention provide systems and methods for storage medium flaw detection. For example, some embodiments provide flaw detection systems that include an input circuit, a data processing circuit and a defect detection circuit. The input circuit is operable to receive an input signal and to provide a filtered output. The data processing circuit is operable to receive the filtered output and to compute a difference between the filtered output and an expected output, and the defect detection circuit receives the difference between the filtered output and the expected output and compares a derivative of the difference with a threshold value, and asserts a defect signal when a magnitude of the derivative of the difference exceeds a threshold value.