SANJAY ARUN PATEL
Medical Practice in Cary, NC

2014004, Feb 6, 2014

Jan 2, 2013

13/733054

Yeshwant Nagaraj Kolla - Wake Forest NC, US
Sanjay B. Patel - Cary NC, US

QUALCOMM INCORPORATED - San Diego CA

G06F 1/32

713322

Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.

6177445, Jan 23, 2001

Dec 22, 1999

9/381721

Eric Cleveland Bigham - Chapel Hill NC
Grady Evan Boswell - Fountain Inn SC
John Joseph Savarese - Southbury CT
Roy Archibald Swaringen - Durham NC
Sanjay Shashikant Patel - Cary NC
Eric Eugene Boros - Chapel Hill NC
Robert Anthony Mook - Chapel Hill NC
Vincente Samano - Chapel Hill NC

Glaxo Wellcome Inc. - Research Triangle Park NC
Cornell Research Foundation Inc. - Ithaca NY

A61K 3147, C07D45502, C07D21702, C07D21700

514308

Ultra short acting neuromuscular blocking agents of Formula (I) which are useful as skeletal muscle relaxants during emergency intubation procedures, routine surgery and post-operative settings are disclosed, wherein q and t are independently from 0 to 4; X. sup. 1 and X. sup. 2 are independently halogen; h. sup. a and h. sup. b are independenity from 0 to 2; Z. sup. 1 and Z. sup. 2 are indepentdently hydrogen, C. sub. 1-6 alkyl, C. sub. 2-6 alkenyl or C. sub. 2-6 alkynyl with the proviso that Z. sup. 1 and Z. sup. 2 are not both hydrogen; Y. sup. 1, Y. sup. 2, and Y. sup. 3 and Y. sup. 4 are independently hydrogen, halogen or C. sub. 1-3 alkoxy; m and p are independently 1 to 6; n and r are independently 0 to 4; with the proviso the if h. sup. a and h. sup. b are both 0, then r is 0 and n is 0 to 2; R. sup. 1 to R. sup. 14 are independently hydrogen, halogen, C. sub.

6187789, Feb 13, 2001

Jan 19, 2000

9/381719

Eric Cleveland Bigham - Chapel Hill NC
Grady Evan Boswell - Cary NC
John Joseph Savarese - Southbury CT
Roy Archibald Swaringen - Durham NC
Sanjay Shashikant Patel - Cary NC
Eric Eugene Boros - Chapel Hill NC
Robert Anthony Mook - Chapel Hill NC
Vincente Samano - Chapel Hill NC

Glaxo Wellcome Inc. - Research Triangle Park NC
Cornell Research Foundation Inc. - Ithaca NY

A61K 3147, C07D21702, C07D21706, C07D21712

514308

Ultrashort acting neuromuscular blocking agents of Formula (I) which are useful as skeletal muscle relaxants during emergency intubation procedures, routine surgery and post-operative settings are disclosed, wherein: X is a halogen; h is from 1 to 2; Y is hydrogen or methoxy; Z. sup. 1 and Z. sup. 2 are methyl; W. sup. 1 and W. sup. 2 are carbon; and A is a pharmaceutically acceptable anion.

7447956, Nov 4, 2008

Mar 3, 2006

11/367959

Lakshmikant Mamileti - Cary NC, US
Anand Krishnamurthy - Morrisville NC, US
Clint Wayne Mumford - Apex NC, US
Sanjay B Patel - Cary NC, US

QUALCOMM Incorporated - San Diego CA

G11C 29/00

714718, 714 5, 714 25, 714 30, 714 42, 714719, 714723, 714724, 714730, 714733, 714734, 714738, 714742, 714799

Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.

7730282, Jun 1, 2010

Aug 11, 2004

10/916188

James N. Dieffenderfer - Apex NC, US
Nathan S. Nunamaker - Durham NC, US
Sanjay B. Patel - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 9/00

712216, 712217

A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.

2006004, Mar 2, 2006

Aug 26, 2004

10/926566

James Dieffenderfer - Apex NC, US
Sanjay Patel - Cary NC, US
Brian Stempel - Raleigh NC, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714038000

A method and system for monitoring the real-time of software running on a microprocessor system. Debug hardware is used to select a range of instructions or events to be monitored by a performance monitor interval with the microprocessor system. A comparison is made between each event and start and stop events are identified in the debug hardware. The performance monitor is enabled by the debug hardware, when events occur within the range defined by the debug hardware. Use of the debug hardware for enabling performance monitoring avoids any overhead associated with generating interrupts, or additional code in the application program.

2011024, Oct 6, 2011

Apr 1, 2010

12/752515

Jeffrey Todd Bridges - Raleigh NC, US
Sanjay B. Patel - Cary NC, US

QUALCOMM Incorporated - San Diego CA

H02J 1/00

307 31

Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

2006015, Jul 13, 2006

Jan 6, 2005

11/030339

James Dieffenderfer - Apex NC, US
Richard Doing - Raleigh NC, US
Sanjay Patel - Cary NC, US
Steven Testa - Durham NC, US
Kenichi Tsuchiya - Cary NC, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F 9/30

712204000

Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.