DR. SANG HOON LEE, M.D.
Osteopathic Medicine at Oconnor Dr, San Jose, CA
License number
California A33164
Category
Osteopathic Medicine
Type
Hematology & Oncology
Address
Address
2
100 Oconnor Dr SUITE 25, San Jose, CA 95128
501 W Hacienda Ave #E2, Campbell, CA 95008
501 W Hacienda Ave #E2, Campbell, CA 95008
Phone
(408) 425-0200
Personal information
See more information about SANG HOON LEE at radaris.comName
Address
Phone
451 Ford Pl, Pasadena, CA 91101
4516 Ramsdell Ave Apt 120, La Crescenta, CA 91214
4516 Earhart Ave, Santa Rosa, CA 95407
4520 Pennsylvania Ave Apt 10, La Crescenta, CA 91214
455 E 3Rd St Apt 1411, Los Angeles, CA 90013
Professional information
Senior Manager Of Technology At Intermolecular Inc.
Position:
Senior Manager of Technology at Intermolecular Inc.
Location:
Fremont, California
Industry:
Renewables & Environment
Work:
Intermolecular Inc.
- San Jose, CA since Oct 2011
-
Senior Manager of Technology
Solyndra
- Fremont, CA May 2008 - Aug 2011
-
Member of Technical Staff
Applied Materials Inc.
- Santa Clara, CA Jan 2006 - May 2008
-
Senior Process Engineer
Physics, North Carolina State University
- Raleigh, NC Sep 2002 - Dec 2005
-
Postdoc Research Associate
Veeco Instruments
- Fort Collins, CO Apr 2001 - Sep 2002
-
Materials Scientist
Education:
University of Houston 1995 - 2001
Ph.D, Chemical Physics Pohang University of Science and Technology 1993 - 1995
M.S, Physical Chemistry Korea University 1987 - 1992
B.S, Chemistry
Ph.D, Chemical Physics Pohang University of Science and Technology 1993 - 1995
M.S, Physical Chemistry Korea University 1987 - 1992
B.S, Chemistry
Sang Lee - San Jose, CA
Work:
Ancoq Corporation
President LG Display America - San Jose, CA
Director, Field Application Engineering National Semiconductor - Santa Clara, CA
Staff Applications Engineer cDream Corp - San Jose, CA
Principal Design Engineer Candescent Technologies - San Jose, CA
Sr. Electrical Engineering Design Engineer Candescent Korea - Korea, VA
Sr. Product Development Engineer LG Display - Korea, VA
Manager of the Technical Assistance Part LG Display - Korea, VA
Manager of the Mass Production Part LG Display - Korea, VA
Manager of the Part LG Display - Korea, VA
Sr. Engineer of X-Task Force Team LG Display - Korea, VA
Sr. Engineer of Task Force Team LG Display - Korea, VA
Project manager of Part (Monitor) LG Display - Korea, VA
Sr. Engineer of S-Task Force Team LG Display - Anyang, Korea
Sr. Engineer of S-Task Force Team LG Display - Anyang, Korea
Specialist of Patent Team LG Display - Anyang, Korea
Engineer of Projector Group LG Display - Anyang, Korea
Engineer of Circuit Design Group
President LG Display America - San Jose, CA
Director, Field Application Engineering National Semiconductor - Santa Clara, CA
Staff Applications Engineer cDream Corp - San Jose, CA
Principal Design Engineer Candescent Technologies - San Jose, CA
Sr. Electrical Engineering Design Engineer Candescent Korea - Korea, VA
Sr. Product Development Engineer LG Display - Korea, VA
Manager of the Technical Assistance Part LG Display - Korea, VA
Manager of the Mass Production Part LG Display - Korea, VA
Manager of the Part LG Display - Korea, VA
Sr. Engineer of X-Task Force Team LG Display - Korea, VA
Sr. Engineer of Task Force Team LG Display - Korea, VA
Project manager of Part (Monitor) LG Display - Korea, VA
Sr. Engineer of S-Task Force Team LG Display - Anyang, Korea
Sr. Engineer of S-Task Force Team LG Display - Anyang, Korea
Specialist of Patent Team LG Display - Anyang, Korea
Engineer of Projector Group LG Display - Anyang, Korea
Engineer of Circuit Design Group
Education:
Konkuk Graduate School - Seoul, Korea
MS in Electronic Engineering Konkuk University - Seoul, Korea
BA in Electronic Engineering
MS in Electronic Engineering Konkuk University - Seoul, Korea
BA in Electronic Engineering
Sang H Lee, San Jose CA
Specialties:
Surgeon
Address:
455 Oconnor Dr, San Jose, CA 95128
Board certifications:
American Board of Thoracic Surgery Certification in Thoracic and Cardiac Surgery (Thoracic Surgery)
Cost-Effective Display Methods And Apparatuses
US Patent:
2013030, Nov 14, 2013
Filed:
May 29, 2013
Appl. No.:
13/904017
Inventors:
Sang Tae Lee - San Jose CA, US
International Classification:
G09G 3/20, G09G 3/36
US Classification:
345691, 345209, 345 96, 345 88
Abstract:
In first aspect of the invention, driving methods of gate interlaced scanning for color LCD are disclosed. This interlaced scanning involves powering odd gate lines sequentially first and then powering even gate lines sequentially, which can minimize the voltage polarity swing to reduce power consumption in source output block. In second aspect of the invention, driving methods of FSCLCD having an RGB LED backlight unit scanning with an increased LED lamp turn on time and reduced potential non-uniformity near modular light guid panel are disclosed. Novel driving methods of variabnt sub-color frame periods are also disclosed with various color sub-frames. In third aspect of the invention, a dual common electrode color LCD with a source driver IC block with lower driving voltage and lower power consumption in the display panel is disclosed, wherein each common electrode voltage has opposite voltage phase to reduce the source driving voltage.
Cost-Effective Display Methods And Apparatuses
US Patent:
2011016, Jul 7, 2011
Filed:
Jan 3, 2011
Appl. No.:
12/983880
Inventors:
Sang Tae Lee - San Jose CA, US
International Classification:
G09G 5/10, G09G 5/02, G09G 3/36
US Classification:
345691, 345698, 345211, 345 87
Abstract:
In first aspect of the invention, driving methods of gate interlaced scanning for color LCD are disclosed. This interlaced scanning involves powering odd gate lines sequentially first and then powering even gate lines sequentially, which can minimize the voltage polarity swing to reduce power consumption in source output block. In second aspect of the invention, driving methods of FSCLCD having an RGB LED backlight unit scanning with an increased LED lamp turn on time and reduced potential non-uniformity near modular light guide panel are disclosed. Novel driving methods of variant sub-color frame periods are also disclosed with various color sub-frames. In third aspect of the invention, a dual common electrode color LCD with a source driver IC block with lower driving voltage and lower power consumption in the display panel is disclosed, wherein each common electrode voltage has opposite voltage phase to reduce the source driving voltage.
Method Of Fabricating High Efficiency Cigs Solar Cells
US Patent:
2013030, Nov 21, 2013
Filed:
Dec 12, 2012
Appl. No.:
13/711860
Inventors:
Sang Lee - San Jose CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Assignee:
INTERMOLECULAR, INC. - San Jose CA
International Classification:
H01L 31/18
US Classification:
438 87
Abstract:
A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25−0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
Method Of Fabricating High Efficiency Cigs Solar Cells
US Patent:
8586457, Nov 19, 2013
Filed:
Aug 27, 2012
Appl. No.:
13/595730
Inventors:
Haifan Liang - Fremont CA, US
Sang Lee - San Jose CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Sang Lee - San Jose CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Assignee:
Intermolecular, Inc. - San Jose CA
International Classification:
H01L 21/20
US Classification:
438509, 438 95, 438478, 438797, 257E21461, 257E31015, 257E2109, 257E31026
Abstract:
A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0. 25−0. 66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
Method Of Fabricating High Efficiency Cigs Solar Cells
US Patent:
2013030, Nov 21, 2013
Filed:
Jan 9, 2013
Appl. No.:
13/737127
Inventors:
Sang Lee - San Jose CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Wei Liu - Sunnyvale CA, US
Sandeep Nijhawan - Los Altos CA, US
Jeroen Van Duren - Palo Alto CA, US
Assignee:
INTERMOLECULAR, INC. - San Jose CA
International Classification:
H01L 31/18
US Classification:
438 87
Abstract:
A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25-0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.
Frequency Synthesizer With Selectable Preconfigured Synthesizer Characteristics
US Patent:
7158760, Jan 2, 2007
Filed:
Aug 22, 2002
Appl. No.:
10/227634
Inventors:
William B. Baringer - Oakland CA, US
Cormac S. Conroy - Sunnyvale CA, US
Sang Oh Lee - San Jose CA, US
Seok Kang - Daejeon, KR
Beomsup Kim - Cupertino CA, US
Cormac S. Conroy - Sunnyvale CA, US
Sang Oh Lee - San Jose CA, US
Seok Kang - Daejeon, KR
Beomsup Kim - Cupertino CA, US
Assignee:
Qualcomm Inc. - San Diego CA
International Classification:
H04B 1/40, H04B 7/00, H04B 1/18
US Classification:
455 76, 455260, 4551501, 4551651
Abstract:
A system and method are disclosed for configuring a frequency synthesizer in a transceiver. Configuring a frequency synthesizer in a transceiver includes specifying a selection bit sequence wherein the selection bit sequence corresponds to a predetermined combination of transceiver characteristics; determining a plurality of synthesizer configuration parameters using the selection bit sequence; and configuring the frequency synthesizer using the plurality of synthesizer configuration parameters.
No Flow Underfill
US Patent:
2012010, May 3, 2012
Filed:
Nov 2, 2010
Appl. No.:
12/938068
Inventors:
Belgacem Haba - Saratoga CA, US
Ilyas Mohammed - Santa Clara CA, US
Ellis Chau - San Jose CA, US
Sang Il Lee - San Jose CA, US
Kishor Desai - Fremont CA, US
Ilyas Mohammed - Santa Clara CA, US
Ellis Chau - San Jose CA, US
Sang Il Lee - San Jose CA, US
Kishor Desai - Fremont CA, US
Assignee:
TESSERA RESEARCH LLC - San Jose CA
International Classification:
H01L 23/48, H01L 21/60
US Classification:
257737, 2281732, 257E23021, 257E2151
Abstract:
A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.