SAMUEL TAYLOR RAY
Pilots at Bryson Ct, Morgan Hill, CA

2002017, Nov 28, 2002

May 25, 2001

09/865830

Samuel Ray - Morgan Hill CA, US

International Business Machines Corporation - Armonk NY

H03K017/56

327/108000

An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of A space allotted by the silicon area on the integrated circuit chip.

7081842, Jul 25, 2006

Oct 18, 2004

10/967756

Louis Lu-Chen Hsu - Fishkill NY, US
James Stephen Mason - Eastleigh, GB
Gareth John Nicholls - Brockenhurst, GB
Philip Murfet - Stockbridge, GB
Samuel Ray - Morgan Hill CA, US

International Business Machines Corporation - Armonk NY

H03M 1/10

341121, 326 30, 326 82, 326 86, 326 90

Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

7812643, Oct 12, 2010

Feb 5, 2009

12/366005

Shashikala Govindu - Union City CA, US
Samuel Taylor Ray - Morgan Hill CA, US

International Business Machines Corporation - Armonk NY

H03K 19/20, H03K 19/094

326115, 327108

A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

7279950, Oct 9, 2007

Sep 27, 2005

11/235758

Stacy J. Garvin - Durham NC, US
Vernon R. Norman - Cary NC, US
Samuel T. Ray - Morgan Hill CA, US
Wayne A. Utter - Fuquay-Varina NC, US

International Business Machines Corporation - Armonk NY

H03K 3/00

327291, 327299

A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

2007027, Dec 6, 2007

Jun 27, 2007

11/769408

Hayden Cranford - Cary NC, US
Stacy Garvin - Durham NC, US
Vernon Norman - Cary NC, US
Samuel Ray - Morgan Hill CA, US
Wayne Utter - Fuquay-Varina NC, US

International Business Machines Corporation - Armonk NY

H03K 3/00

327291000

A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.