Sai Chong Kwok
Engineers at Mesa Oak Pl, Escondido, CA
License number
Colorado 35128
Issued Date
Jan 24, 2001
Renew Date
Feb 1, 2005
Expiration Date
Jan 31, 2007
Type
Professional Engineer
Address
Address
2247 Mesa Oak Pl, Escondido, CA 92027
Personal information
See more information about Sai Chong Kwok at radaris.comName
Address
Phone
2247 Mesa Oak Pl, Escondido, CA 92027
7972 Eclipse Rd, San Diego, CA 92129
PO Box 928167, San Diego, CA 92192
115 San Pedro St, San Pablo, CA 94806
3771 Mission St, San Francisco, CA 94110
Professional information
See more information about Sai Chong Kwok at trustoria.com
Methods And Apparatus For Power Reduction In A Transceiver
Methods And Apparatus For Power Reduction In A Transceiver
US Patent:
8565669, Oct 22, 2013
Filed:
Jun 2, 2008
Appl. No.:
12/131800
Inventors:
Prasad S Gudem - San Diego CA, US
Steven C Ciccarelli - San Diego CA, US
Ken Tsz Kin Mok - San Diego CA, US
Sai C. Kwok - Escondido CA, US
Steven C Ciccarelli - San Diego CA, US
Ken Tsz Kin Mok - San Diego CA, US
Sai C. Kwok - Escondido CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H04K 3/00
US Classification:
455 1, 455 6711, 455296, 327170, 330289, 330291
Abstract:
An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.
Common Mode Signal Attenuation For A Differential Duplexer
Common Mode Signal Attenuation For A Differential Duplexer
US Patent:
7848713, Dec 7, 2010
Filed:
Sep 28, 2007
Appl. No.:
11/864338
Inventors:
Jose Cabanillas - San Diego CA, US
Prasad S. Gudem - San Diego CA, US
Sai Chong Kwok - Escondido CA, US
David Love - San Diego CA, US
Prasad S. Gudem - San Diego CA, US
Sai Chong Kwok - Escondido CA, US
David Love - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H04B 1/46
US Classification:
455 83, 455 78, 455 82, 4552481, 343861
Abstract:
Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX− ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX− ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX− port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground.
Frequency Calibration Of Radio Frequency Oscillators
Frequency Calibration Of Radio Frequency Oscillators
US Patent:
8130046, Mar 6, 2012
Filed:
Mar 19, 2009
Appl. No.:
12/407666
Inventors:
Sai C. Kwok - Escondido CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03L 7/00
US Classification:
331 16, 331 1 A, 331117 R
Abstract:
A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored.
Switching Voltage Regulator With Frequency Selection
Switching Voltage Regulator With Frequency Selection
US Patent:
8294445, Oct 23, 2012
Filed:
Dec 4, 2008
Appl. No.:
12/327990
Inventors:
Sai C. Kwok - Escondido CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03G 5/24, H03G 5/28
US Classification:
323283, 323224, 323351, 323284
Abstract:
Techniques for mitigating interference from a switching voltage regulator by intelligently varying the switcher frequency of the switching voltage regulator are provided. In one aspect, the switcher frequency is set by adjusting a frequency setting input to a programmable clock divider. In a further aspect, a processor drives a programmable clock divider which receives a value representative of a dividing factor by which to divide a reference clock frequency signal to generate a desired switcher frequency for the switching voltage regulator. Values of the programmable clock divider are selectively varied to achieve optimal performance and mitigate the effect of switcher frequency spurious content for a given operating condition or conditions.