RYAN LANE
Marriage and Family Therapists at Viewridge Ave, San Diego, CA
License number
California IMF95232
Category
Marriage and Family Therapists
Type
Marriage & Family Therapist
Address
Address
2
4660 Viewridge Ave, San Diego, CA 92123
7 Larry Ln, Escondido, CA 92025
7 Larry Ln, Escondido, CA 92025
Phone
(858) 278-3292
(760) 215-3595
(760) 215-3595
Personal information
See more information about RYAN LANE at radaris.comName
Address
Phone
5425 Snyder Ln, Rohnert Park, CA 94928
530 Nottingham Dr, Redlands, CA 92373
433A Patricia Ave, San Mateo, CA 94401
714 Cohasset Ct, San Diego, CA 92109
7518 Dunbarton Ave, Los Angeles, CA 90045
Professional information
Marketing Research Consultant At Medimpact
Position:
Marketing Research Consultant at MedImpact
Location:
Greater San Diego Area
Industry:
Pharmaceuticals
Work:
MedImpact
- Greater San Diego Area since Jul 2011
-
Marketing Research Consultant
Pharmatek Laboratories, Inc.
- Greater San Diego Area Sep 2010 - Jul 2011
-
Marketing Associate
Pharmatek Laboratories, Inc.
Oct 2006 - Aug 2010
-
Marketing Coordinator
Kugan & Associates, LLC
Feb 2005 - Aug 2008
-
Consultant
San Diego State University
Feb 2006 - May 2007
-
Telecommunications and Network Services Helpdesk Analyst
Kelar Corporation
Oct 2001 - Jul 2005
-
Marketing Associate
Maxim Pharmaceuticals
Aug 2000 - Sep 2001
-
Laboratory Assistant
Education:
San Diego State University-California State University 2005 - 2007
San Diego Mesa College 2003 - 2005
Palomar College 2001 - 2003
San Diego Mesa College 2003 - 2005
Palomar College 2001 - 2003
Skills:
CRM, SEO, Web Marketing, Webmaster Services, Database Admin, Pharmaceutical Industry, Market Research, Product Development, Salesforce.com, Biotechnology, Medical Devices, Marketing Strategy
Method To Optimize And Reduce Integrated Circuit, Package Design, And Verification Cycle Time
US Patent:
2012006, Mar 22, 2012
Filed:
Sep 22, 2010
Appl. No.:
12/887556
Inventors:
Ryan D. Lane - San Diego CA, US
Ruey Kae Zang - San Diego CA, US
Ruey Kae Zang - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H01L 23/48, H01L 21/66
US Classification:
257 48, 438 15, 257E21521, 257E2301
Abstract:
A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
Hybrid Package Construction With Wire Bond And Through Silicon Vias
US Patent:
2011011, May 19, 2011
Filed:
Nov 18, 2009
Appl. No.:
12/620971
Inventors:
Ratibor Radojcic - San Diego CA, US
Arvind Chandrasekaran - San Diego CA, US
Ryan Lane - San Diego CA, US
Arvind Chandrasekaran - San Diego CA, US
Ryan Lane - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H01L 23/52, H01L 23/538, H01L 21/60
US Classification:
257686, 257776, 438121, 257691, 257784, 257E21509, 257E23141, 257E23169
Abstract:
A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.
Director, Engineering
Position:
Director, Engineering at Qualcomm
Location:
Greater San Diego Area
Industry:
Semiconductors
Work:
Qualcomm
since May 2000
-
Director, Engineering
Skills:
IC, ASIC, SoC
Director, Engineering
Position:
Director, Engineering at Qualcomm
Location:
Greater San Diego Area
Industry:
Semiconductors
Work:
Qualcomm
since May 2000
-
Director, Engineering
Ryan Lane
Location:
Greater San Diego Area
Industry:
Marketing and Advertising
Radio Frequency Package On Package Circuit
US Patent:
2013012, May 16, 2013
Filed:
Nov 14, 2012
Appl. No.:
13/677054
Inventors:
Gurkanwal Singh Sahota - San Diego CA, US
Steven C Ciccarelli - San Diego CA, US
David J Wilding - San Diego CA, US
Ryan D Lane - San Diego CA, US
Christian Holenstein - La Mesa CA, US
Milind P Shah - San Diego CA, US
Steven C Ciccarelli - San Diego CA, US
David J Wilding - San Diego CA, US
Ryan D Lane - San Diego CA, US
Christian Holenstein - La Mesa CA, US
Milind P Shah - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H05K 3/36, H05K 13/04, H04B 1/40
US Classification:
455 902, 29830, 29738
Abstract:
A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.
Method For Accommodating Small Minimum Die In Wire Bonded Area Array Packages
US Patent:
2004019, Oct 7, 2004
Filed:
Apr 21, 2004
Appl. No.:
10/830188
Inventors:
Ryan Lane - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US
International Classification:
H01L027/082, H01L027/102, H01L029/70, H01L031/11, H01L023/48, H01L023/52, H01L029/40
US Classification:
257/784000
Abstract:
An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.
Optimized Power Delivery To High Speed, High Pin-Count Devices
US Patent:
7612449, Nov 3, 2009
Filed:
Dec 28, 2004
Appl. No.:
11/025486
Inventors:
Justin Joseph Rosen Gagne - San Diego CA, US
Mark Stephen Veatch - San Diego CA, US
Ryan Lane - San Diego CA, US
Mark Stephen Veatch - San Diego CA, US
Ryan Lane - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H01L 23/52
US Classification:
257738, 257E23021, 438613
Abstract:
A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed at the periphery and electrically connected to the substrate ground via.
Method For Accommodating Small Minimum Die In Wire Bonded Area Array Packages
US Patent:
6891275, May 10, 2005
Filed:
Jul 21, 2003
Appl. No.:
10/624787
Inventors:
Ryan Lane - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H01L029/40
US Classification:
257786, 257737
Abstract:
An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.