RYAN LANE
Marriage and Family Therapists at Viewridge Ave, San Diego, CA

2012006, Mar 22, 2012

Sep 22, 2010

12/887556

Ryan D. Lane - San Diego CA, US
Ruey Kae Zang - San Diego CA, US

QUALCOMM INCORPORATED - San Diego CA

H01L 23/48, H01L 21/66

257 48, 438 15, 257E21521, 257E2301

A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.

2011011, May 19, 2011

Nov 18, 2009

12/620971

Ratibor Radojcic - San Diego CA, US
Arvind Chandrasekaran - San Diego CA, US
Ryan Lane - San Diego CA, US

QUALCOMM INCORPORATED - San Diego CA

H01L 23/52, H01L 23/538, H01L 21/60

257686, 257776, 438121, 257691, 257784, 257E21509, 257E23141, 257E23169

A hybrid interconnect includes a through silicon via and a wire bond. Hybrid interconnects enable better layout of a stacked IC by combining benefits from both interconnect technologies. In one hybrid interconnect, wire bonds couples a second tier die mounted on a first tier die to a redistribution layer in the first tier die. Through silicon vias in the first tier die are coupled to the wire bonds to provide communication. In another hybrid interconnect, a wire bond couples a redistribution layer on a first tier die to a packaging substrate on which the first tier die is mounted. The redistribution layer couples to a second tier die mounted on the first tier die to provide a power supply to the second tier die. Through silicon vias in the first tier die couple to the second tier die to provide communication from the packaging substrate to the second tier die.

2013012, May 16, 2013

Nov 14, 2012

13/677054

Gurkanwal Singh Sahota - San Diego CA, US
Steven C Ciccarelli - San Diego CA, US
David J Wilding - San Diego CA, US
Ryan D Lane - San Diego CA, US
Christian Holenstein - La Mesa CA, US
Milind P Shah - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H05K 3/36, H05K 13/04, H04B 1/40

455 902, 29830, 29738

A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.

2004019, Oct 7, 2004

Apr 21, 2004

10/830188

Ryan Lane - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US

H01L027/082, H01L027/102, H01L029/70, H01L031/11, H01L023/48, H01L023/52, H01L029/40

257/784000

An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.

7612449, Nov 3, 2009

Dec 28, 2004

11/025486

Justin Joseph Rosen Gagne - San Diego CA, US
Mark Stephen Veatch - San Diego CA, US
Ryan Lane - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H01L 23/52

257738, 257E23021, 438613

A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed at the periphery and electrically connected to the substrate ground via.

6891275, May 10, 2005

Jul 21, 2003

10/624787

Ryan Lane - San Diego CA, US
Edward Reyes - San Diego CA, US
Mark Veatch - San Diego CA, US
Tom Gregorich - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H01L029/40

257786, 257737

An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.