RUEDIGER HELD
Pilots at 22 Ave, Minneapolis, MN

6780771, Aug 24, 2004

Jan 23, 2001

09/768873

Venuka K. Jayatilaka - Farmington MN
Matthew D. Buchanan - Edina MN
Ruediger Held - Minneapolis MN

Cypress Semiconductor Corp. - San Jose CA

H01L 21302

438690, 438691, 438692

A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

6761619, Jul 13, 2004

Jul 10, 2001

09/902837

Ruediger Held - Minneapolis MN

Cypress Semiconductor Corp. - San Jose CA

B24B 100

451 41, 451288, 438691

A method is provided for processing a semiconductor topography. In an embodiment, the method includes positioning a semiconductor topography against a carrier plate with a raised section. Such a method preferably allows a larger area capable of producing a target yield of semiconductor devices within dimensional specifications to be obtained than is obtained by positioning the topography against a carrier plate with a flat surface. As such, positioning a topography against a carrier plate with one or more raised sections may form a substantially planar upper surface in a larger area than in an area formed by positioning such a topography against a flat surface carrier plate. Furthermore, such a method is preferably conducted in a single polishing step. As such, a polishing system is provided which includes a carrier plate with a raised section adapted to planarize a semiconductor topography in one polishing step.

6509270, Jan 21, 2003

Mar 30, 2001

09/823530

Ruediger Held - Minneapolis MN

Cypress Semiconductor Corp. - San Jose CA

H01L 21302

438691, 438690, 438692, 438693

A method is provided for processing a semiconductor topography. In particular a method is provided in which a greater pressure may be applied to a first portion of a semiconductor topography than in a second portion of the topography. As such, a method is provided in which a portion of an upper layer in a region adjacent to an outer edge of the semiconductor topography is polished at a faster rate than a portion of the upper layer in a region comprising the center of the topography. Consequently, the method may subsequently provide a manner in which a substantially planar upper surface may be formed across a semiconductor topography including a region adjacent to an outer edge of the semiconductor topography. Alternatively, regions of an upper layer of a semiconductor topography polished at a faster rate than other regions may occur at various locations across the topography.

6786809, Sep 7, 2004

Mar 30, 2001

09/823446

Ruediger Held - Minneapolis MN

Cypress Semiconductor Corp. - San Jose CA

B24B 100

451288, 451398, 451286, 451289

A CMP system, a wafer carrier, and components of a wafer carrier are provided for processing a semiconductor topography. In particular, a CMP system, a wafer carrier, and components of a wafer carrier are provided in which a greater pressure may be applied in a first portion of a semiconductor topography than in a second portion of the topography. The first portion may, for example, be adjacent to an outer edge of the topography, while the second portion may include the center of the topography. Alternatively, the first portion and second portion of the semiconductor topography may include any region of the topography. The wafer carrier components may include a carrier plate and/or a carrier backing film adapted to apply a greater pressure in a first portion of the semiconductor topography than in a second portion of the semiconductor topography.

7157792, Jan 2, 2007

Sep 15, 2003

10/662636

Venuka K. Jayatilaka - Farmington MN, US
Matthew D. Buchanan - Edina MN, US
Ruediger Held - Minneapolis MN, US

Cypress Semiconductor Corp. - San Jose CA

H01L 23/053, H01L 23/12, H01L 23/04

257701, 257730, 257E23167

A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

6866571, Mar 15, 2005

May 21, 2002

10/152590

Ruediger Held - Minneapolis MN, US

Cypress Semiconductor Corp. - San Jose CA

B24B041/06

451390, 451285, 451398

A polishing system is provided which includes an o-ring adapted to couple a carrier ring to a carrier plate. In some embodiments, one component may include a groove with which to receive the o-ring and the other component may be substantially absent of a groove adapted to receive an o-ring. Alternatively, both components may include a groove with which to receive the o-ring. Consequently, a semiconductor polishing system component comprising a notch adapted to receive an o-ring is also provided herein. In particular, the semiconductor polishing system component may be adapted to couple to another semiconductor polishing system component by use of the o-ring. In addition, a method for assembling a semiconductor polishing system is contemplated herein, which includes positioning a first component of the semiconductor polishing system against a portion of an o-ring protruding from a groove arranged within a second component of the semiconductor polishing system.