ROY WALTER LEWALLEN
Pilots at 152 Ave, Beaverton, OR

License number
Oregon A4834365
Issued Date
Mar 2016
Expiration Date
Mar 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
5470 SW 152Nd Ave, Beaverton, OR 97007

Personal information

See more information about ROY WALTER LEWALLEN at radaris.com
Name
Address
Phone
Roy W Lewallen, age 78
5470 152Nd Ave, Beaverton, OR 97007
(503) 671-9046
(503) 646-2885
Roy W. Lewallen
Beaverton, OR
(503) 646-2885

Professional information

Roy Lewallen Photo 1

Method For Reducing Harmonic Distortion In An Analog-To-Digital Converter System

US Patent:
5629703, May 13, 1997
Filed:
Aug 9, 1995
Appl. No.:
8/512797
Inventors:
Roy W. Lewallen - Beaverton OR
Assignee:
Tektronix, Inc. - Wilsonville OR
International Classification:
H03M 112
US Classification:
341155
Abstract:
A spectrum analyzer (10, 70) employs a method of reducing the amplitude of harmonic and spurious signals (102, 104, 112) introduced into a frequency-domain output spectrum by, for example, nonlinearities in a mixer (12, 78) or an ADC (20, 92). The method employs acquiring and digitizing a normal time-domain data record of an input signal, transforming the time-domain data record to a normal frequency-domain record (30), and storing the normal record. Next, a local oscillator (14, 76) driving the mixer is frequency shifted, and an additional time-domain data record is acquired, digitized, transformed, and stored to produce a shifted frequency-domain data record (40). Then, the shifted data record is mathematically realigned (50) with the normal data record and the normal and realigned data records are combined to produce a frequency-domain data record (60) having reduced harmonic and spurious signal amplitudes. The method preferably employs multiple frequency shifts of the local oscillator and a corresponding number of acquisitions, digitizations, transformations, realignments, and averages.


Roy Lewallen Photo 2

Method And Apparatus For Prescaler Desynchronization

US Patent:
5122734, Jun 16, 1992
Filed:
Jul 19, 1990
Appl. No.:
7/555212
Inventors:
Roy W. Lewallen - Beaverton OR
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
G01R 1320, H03K 1700
US Classification:
324121R
Abstract:
A method and apparatus prevents unwanted synchronization from obstructing a data acquisition instrument operator's view of N multiplexed signals synchronized to a high speed system clock being used to trigger an instrument through a prescaler with a fixed prescaling factor M, where N and M are related by a common factor. During a time while the instrument, for example, an oscilloscope, is ignoring trigger input information, a desynchronizing signal is applied to the prescaler, causing it to miss a random number of counts or causing it to count incorrectly. Thus, when the oscilloscope resumes triggering it is likely to be synchronized to a different combination of the multiplexed signals. This technique can be applied to individual data points or to records containing a number of data points. By accumulating a number of records obtained in this way and superimposing them on the display, or by simply displaying them very rapidly so that the averaging effects of the human eye cause them to appear to be superimposed, these composite records effectively include complete information about the full set of multiplexed signals.


Roy Lewallen Photo 3

High Speed Step Generator Output Circuit

US Patent:
4924110, May 8, 1990
Filed:
Sep 8, 1988
Appl. No.:
7/241686
Inventors:
John B. Rettig - Portland OR
Jonathan Lueker - Portland OR
John E. Carlson - Portland OR
Stanley P. Kaveckis - Aurora OR
Roy W. Lewallen - Beaverton OR
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H03K 402, H03K 512, H03K 501, H03K 1756
US Classification:
307227
Abstract:
A step generator for producing steps having constant edge parameters while driving varying loads includes a pair of DC coupled low speed diode switches for slowly switching the output load current. A pair of capacitors provide an AC coupled high speed input for rapidly, but temporarily, switching the output load current until the sustaining action of the low speed diode switch has occurred. A pair of resistor divider circuits in each of the low speed diode switches maintains a relatively constant reverse bias voltage across the diodes coupled to the capacitors. The high speed switching threshold is maintained at a relatively constant level which produces an output voltage step with constant edge parameters and no overshoot.