Ronald Harley Cox
Engineers at Edgewater Dr, Plano, TX

License number
Colorado 5221
Issued Date
Dec 7, 1963
Renew Date
Feb 23, 1985
Expiration Date
Feb 23, 1985
Type
Professional Engineer
Address
Address
1929 Edgewater Dr, Plano, TX 75075
LicenseFiles verified this license of Dec 9, 2016 at the Colorado - Department of Regulatory Agencies.

Professional information

Ronald Cox Photo 1

Fine Pitch System And Method For Reinforcing Bond Pads In Semiconductor Devices

US Patent:
6818540, Nov 16, 2004
Filed:
Jul 23, 2002
Appl. No.:
10/201725
Inventors:
Mukul Saran - Richardson TX
Charles A. Martin - Melissa TX
Ronald H. Cox - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2144
US Classification:
438612, 438622, 438623, 438637
Abstract:
A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

Ronald Cox Photo 2

Fine Pitch System And Method For Reinforcing Bond Pads In Semiconductor Devices

US Patent:
6448650, Sep 10, 2002
Filed:
May 14, 1999
Appl. No.:
09/312385
Inventors:
Mukul Saran - Richardson TX
Charles A. Martin - Melissa TX
Ronald H. Cox - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2352
US Classification:
257758, 257750, 257763, 257786, 257773, 257774, 257775
Abstract:
A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

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