Roger Lane Jackson
Dentist at Main St, Longmont, CO

License number
Colorado 6543
Issued Date
Sep 21, 1988
Renew Date
Feb 28, 1998
Expiration Date
Feb 28, 1998
Type
Dentist
Address
Address
515 Main St STE B, Longmont, CO 80501

Professional information

Roger Jackson Photo 1

Bay Packing Method And Integrated Circuit Employing Same

US Patent:
4593362, Jun 3, 1986
Filed:
May 16, 1983
Appl. No.:
6/495021
Inventors:
Paul H. Bergeron - Chittenden County VT
Kurt D. Carpenter - Chittenden County VT
Jerome B. Hickson - Yorktown Heights NY
Roger K. Jackson - Longmont CO
Keith W. Lallier - Chittenden County VT
Elba K. Malone - Chittenden County VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1546
US Classification:
364488
Abstract:
A wire packing method for packing wire segments in wiring bays of large-scale integrated circuit devices and integrated circuit devices produced employing such a method. Each wiring segment to be placed in a channel of a wiring bay is assigned a score in accordance with criteria developed for the particular application. The start point, end point and a segment identifier is recorded for each segment to be packed. For each channel, segments which can be considered candidates for packing in that channel are extracted from the list. For that channel, moving forwardly from one end of the channel, at the end point of each segment, a total score is calculated by adding to the score of that segment a best score occurring before the start point of the segment. If the total score exceeds a present value of a best string score for nonoverlapping segments, the present value of the best string score is replaced by the new total score, otherwise the present value of the best string score is retained. When the other end of the bay is reached, moving back towards the first end, segments are assigned to the channel for which the total score therefor exceeded the then-present value of the best string score and which do not overlap already-assigned segments.


Roger Jackson Photo 2

Progressive Insertion Placement Of Elements On An Integrated Circuit

US Patent:
4754408, Jun 28, 1988
Filed:
Nov 21, 1985
Appl. No.:
6/800569
Inventors:
Kurt D. Carpenter - Essex Junction VT
Roger K. Jackson - Longmont CO
Keith W. Lallier - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1560
US Classification:
364491
Abstract:
A method of placing circuit elements in an integrated circuit. The chip area is divided into a grid. In an initial pass, the elements are randomly placed in the grid locations, and these placements are recorded. Thereafter, the elements are sequentially replaced in each of the grid locations, and a score is calculated for the wiring interconnections to the remaining elements as they were last recorded. The placement yielding the best score is recorded for that element. This placement is repeated for each of the elements. Once all the elements have been replaced, a final score is compared with the last best score. If the recent final score is better, the placements associated with that score are saved as the best placements. Then the process of replacement is repeated until a given number of iterations fails to yield a better score.