ROBERT WILLIAM ELLIS
Pilots at San Miguel Ave, Phoenix, AZ

License number
Arizona A2302202
Issued Date
Jan 2017
Expiration Date
Jan 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
134 E San Miguel Ave, Phoenix, AZ 85012

Professional information

Robert Ellis Photo 1

Method And Apparatus For Adjusting Timing Signal Between Media Controller And Storage Media

US Patent:
7512751, Mar 31, 2009
Filed:
Jan 26, 2005
Appl. No.:
11/043709
Inventors:
Robert W. Ellis - Phoenix AZ, US
Kevin L. Kilzer - Chandler AR, US
Daniel P. Fogelson - Chandler AZ, US
Alan A. Fitzgerald - Gilbert AZ, US
Assignee:
Adtron Corporation - Phoenix AZ
International Classification:
G06F 12/00
US Classification:
711154, 710 23
Abstract:
A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command.


Robert Ellis Photo 2

Strategic Development Engineer At Adtron Corporation

Position:
Strategic Development Engineer at Adtron Corporation
Location:
Phoenix, Arizona Area
Industry:
Computer Hardware
Work:
Adtron Corporation - Strategic Development Engineer


Robert Ellis Photo 3

Arrayed Data Storage Architecture With Simultaneous Command Of Multiple Storage Media

US Patent:
2003021, Nov 13, 2003
Filed:
Aug 12, 2002
Appl. No.:
10/217167
Inventors:
Robert Ellis - Phoenix AZ, US
Kevin Kilzer - Chandler AZ, US
Daniel Fogelson - Chandler AZ, US
Alan Fitzgerald - Gilbert AZ, US
International Classification:
G06F012/00
US Classification:
711/114000, 711/154000, 711/131000
Abstract:
A storage system controller () includes a plurality of media controllers (), a local microprocessor (), and a host interface logic (), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus includes a control bus (), a payload data bus (), a real-time ready-status (data ready) signaling bus () and a general microprocessor bus (). Each media controller has a storage media () operably coupled thereto. Each media controller includes a parameter storage (), a media interface circuit (), a control data state machine (), a command sequencer state machine (), a media-side multi-mode transfer state machine (), a dual-port memory (), a memory controller (), and a host-side transfer state machine (). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.


Robert Ellis Photo 4

Storage Control System With Data Management Mechanism And Method Of Operation Thereof

US Patent:
2013033, Dec 12, 2013
Filed:
Jun 11, 2012
Appl. No.:
13/493949
Inventors:
Robert W. Ellis - Phoenix AZ, US
Assignee:
SMART Storage Systems, Inc. - Chandler AZ
International Classification:
G06F 12/00, G06F 11/10, H03M 13/05
US Classification:
714763, 711154, 711E12001, 714E11034
Abstract:
A method of operation of a storage control system includes: generating encoded data having a proportional data distribution for writing to a memory device; identifying a marginal block when an erase block is read from the memory device; and generating a marginal tag for the marginal block, the marginal tag having a non-proportional data distribution different from the proportional data distribution.


Robert Ellis Photo 5

Flash Blade System Architecture And Method

US Patent:
2011003, Feb 10, 2011
Filed:
Aug 10, 2010
Appl. No.:
12/853953
Inventors:
Alan A. Fitzgerald - Gilbert AZ, US
Robert W. Ellis - Phoenix AZ, US
Scott Harrow - Scottsdale AZ, US
Assignee:
ADTRON, INC. - Phoenix AZ
International Classification:
G06F 12/00, G06F 12/02
US Classification:
711103, 711E12001, 711E12008
Abstract:
A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings.


Robert Ellis Photo 6

Data Storage System With Power Cycle Management And Method Of Operation Thereof

US Patent:
2012031, Dec 13, 2012
Filed:
Jun 11, 2012
Appl. No.:
13/493912
Inventors:
Robert W. Ellis - Phoenix AZ, US
Scott Creasman - Gilbert AZ, US
Assignee:
SMART STORAGE SYSTEMS, INC. - Chandler AZ
International Classification:
G06F 11/30, G06F 12/00
US Classification:
713340
Abstract:
A method of operation of a data storage system includes: providing a power monitor module for detecting a loss of host power; interrupting a unit controller by the power monitor module; configuring a memory controller by the unit controller; and writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power.


Robert Ellis Photo 7

Deliberate Destruction Of Integrated Circuits

US Patent:
8149012, Apr 3, 2012
Filed:
Sep 24, 2010
Appl. No.:
12/890436
Inventors:
Robert Lazaravich - Chandler AZ, US
Hugh Littlebury - Gilbert AZ, US
Robert William Ellis - Phoenix AZ, US
Assignee:
SMART Storage Systems, Inc. - Chandler AZ
International Classification:
H03K 19/00
US Classification:
326 8, 326 37
Abstract:
A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device.


Robert Ellis Photo 8

Electronic System With Storage Management Mechanism And Method Of Operation Thereof

US Patent:
2013005, Feb 28, 2013
Filed:
Aug 21, 2012
Appl. No.:
13/590826
Inventors:
Robert W. Ellis - Phoenix AZ, US
James Fitzpatrick - Sudbury MA, US
James Higgins - Chandler AZ, US
Assignee:
SMART STORAGE SYSTEMS, INC. - Chandler AZ
International Classification:
G06F 12/00
US Classification:
711103, 711E12008
Abstract:
A method of operation of an electronic system includes: forming a superblock by organizing an erase block according to a wear attribute; detecting a trigger count of the wear attribute of the superblock; updating a metadata table with the trigger count; and triggering a recycling event of the superblock based on the metadata table.


Robert Ellis Photo 9

Flash Management Using Logical Page Size

US Patent:
8180954, May 15, 2012
Filed:
Apr 15, 2009
Appl. No.:
12/424461
Inventors:
Kevin L Kilzer - Chandler AZ, US
Robert W Ellis - Phoenix AZ, US
Rudolph J Sterbenz - Chandler AZ, US
Assignee:
SMART Storage Systems, Inc. - Chandler AZ
International Classification:
G06F 12/00
US Classification:
711103, 711E12001, 711E12008
Abstract:
Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip.


Robert Ellis Photo 10

Flash Management Using Sequential Techniques

US Patent:
8566505, Oct 22, 2013
Filed:
Apr 15, 2008
Appl. No.:
12/103273
Inventors:
Kevin L. Kilzer - Chandler AZ, US
Robert W. Ellis - Phoenix AZ, US
Rudolph J. Sterbenz - Chandler AZ, US
Assignee:
SMART Storage Systems, Inc. - Chandler AZ
International Classification:
G06F 12/00, G06F 13/00
US Classification:
711103, 711100, 711154
Abstract:
Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.