ROBERT WENZEL
Electrician at Paul E Anderson Dr, Austin, TX

7553753, Jun 30, 2009

Aug 31, 2006

11/469158

George R. Leal - Cedar Park TX, US
Robert J. Wenzel - Austin TX, US
Scott K. Pozder - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/44

438614, 257E21503

A method of forming an embedded device build-up package () includes forming a first plurality of features () over a packaging substrate (), wherein the first plurality of features () comprises a first feature and a second feature, forming at least a first crack arrest feature () in a first crack arrest available region (), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features () over the first plurality of features () wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature () in a second crack arrest available region (), wherein the second crack arrest feature () is between the third feature and the fourth feature, and the second crack arrest feature () is substantially orthogonal to the first crack arrest feature ().

7405102, Jul 29, 2008

Jun 9, 2006

11/450667

Tien Yu T. Lee - Phoenix AZ, US
Craig S. Amrine - Tempe AZ, US
Victor A. Chiriac - Phoenix AZ, US
Lizabeth Ann Keser - Chandler AZ, US
George R. Leal - Cedar Park TX, US
Robert J. Wenzel - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438106, 438127

A multi-layer structure () includes a first build-up layer structure () configured to connect to a heat-generating module (), a second build-up layer structure () configured to connect to a substrate, and a middle layer () provided between the first build-up layer structure and the second build-up layer structure, the middle layer including at least one semiconductor component () and a heat spreader (). A first set of thermal vias () extend through the first build-up layer structure to the heat spreader, and a second set of thermal vias ( extend through the second build-up layer structure to the heat spreader, wherein at least a portion of the first set of thermal vias is in thermal contact with the heat-generating module.

7892882, Feb 22, 2011

Jun 9, 2006

11/450070

George R. Leal - Cedar Park TX, US
Victor A. Chiriac - Phoenix AZ, US
Tien Yu T. Lee - Phoenix AZ, US
Marc A. Mangrum - Manchaca TX, US
Robert J. Wenzel - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/00

438106, 257678

A package assembly includes a semiconductor die (e. g. , an RF power amplifier) fixed within the cavity of a conductive leadframe using a thermally and electrically-conductive adhesive material. The semiconductor die has a first side and a second side, wherein the first side includes at least one active area, and the second side includes at least one contact region. The conductive leadframe (e. g. , a copper leadframe) has two planar surfaces and a cavity formed therein. The adhesive material is configured to couple the semiconductor die within the cavity of the conductive leadframe such that the first side of the semiconductor die is substantially coplanar with the first surface of the conductive leadframe.

6921975, Jul 26, 2005

Apr 18, 2003

10/418790

George R. Leal - Cedar Park TX, US
Edward R. Prack - Austin TX, US
Robert J. Wenzel - Austin TX, US
Brian D. Sawyer - Mesa AZ, US
David G. Wontor - Austin TX, US
Marc Alan Mangrum - Manchaca TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L023/538, H01L023/48

257723, 257686, 257685, 257777, 257684, 257796, 257712, 257713, 257691, 257698

A circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). At least a portion of the conductive layer () may be used as a reference voltage plane (e. g. a ground plane). Additionally, a circuit device () may be placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). The conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive or electrically non-conductive.

6838776, Jan 4, 2005

Apr 18, 2003

10/418763

George R. Leal - Cedar Park TX, US
Edward R. Prack - Austin TX, US
Robert J. Wenzel - Austin TX, US
Brian D. Sawyer - Mesa AZ, US
David G. Wontor - Austin TX, US
Marc Alan Mangrum - Manchaca TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 2940, H01L 2328

257783, 257723, 257787, 438106

In one embodiment, circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). In this embodiment, at least a portion of the conductive layer () may be used as a reference voltage plane (e. g. a ground plane). In one embodiment, circuit device () is placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). In this embodiment, conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

8072062, Dec 6, 2011

Feb 28, 2008

12/039434

George R. Leal - Cedar Park TX, US
Edward R. Prack - Austin TX, US
Robert J. Wenzel - Austin TX, US
Brian D. Sawyer - Mesa AZ, US
David G. Wontor - Austin TX, US
Marc Alan Mangrum - Manchaca TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/34

257723, 257678, 257691, 257724, 257773, 257776, 257783, 257787, 257E23178, 257E21513, 257E21514

A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e. g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

7528069, May 5, 2009

Nov 7, 2005

11/267975

Robert J. Wenzel - Austin TX, US
George R. Leal - Cedar Park TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 21/44

438669, 257E23019, 438612

Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent contact pads are present in the same opening in the dielectric. The traces to the contact pads are in a line so that no widening is required where the lines make contact to the contact pads. The lines can be widened before they get to the contact pads but at the contact pads, they are substantially at the minimum width for the line. Thus, the contact pads can be at a pitch much lower than if capture pads were used.

2013019, Aug 1, 2013

Jan 31, 2012

13/362636

ROBERT J. WENZEL - Austin TX, US
Kevin J. Hess - Austin TX, US
Chu-Chung Lee - Round Rock TX, US

H01L 23/49, H01L 21/56

257784, 438127, 257E23024, 257E21502

A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

7834466, Nov 16, 2010

Dec 17, 2007

11/957838

Robert J. Wenzel - Austin TX, US
Trung Q Duong - Austin TX, US
Ilan Lidsky - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/48, H01L 23/52, H01L 29/40

257786, 257779, 257780, 257E2302

A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads.

7763976, Jul 27, 2010

Sep 30, 2008

12/242550

Jinbang Tang - Chandler AZ, US
Darrel R. Frear - Phoenix AZ, US
Robert J. Wenzel - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

H01L 23/34

257725, 257678, 257723, 257724

A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.