ROBERT TYLER REED
Pilots at Linda Vis Rd, San Diego, CA

5636248, Jun 3, 1997

Oct 4, 1994

8/319146

Harvey Tash - San Diego CA
Robert C. Reed - San Diego CA

The United States of America as represented by the Secretary of the Navy - Washington DC

H04L 2710

375282

The present invention provides a system and method for using a single digzed component of an analog signal to be converted into a pair of digital signals used to re-establish the analog signal. A low level serial transceiver transforms a first analog signal into a first digital signal representing the complement of the first analog signal. The first digital signal is propagated through an electronic interface circuit such as a matrix switch or through some electronic circuit used to detect characteristics of the analog signal. In response to receiving the first digital signal, a logic circuit generates a second digital signal representing the analog signal, and also outputs the first digital signal. In response to receiving the first and second digital signals, a retimer generates a third digital signal comprising a series of pulses. Each of the pulses of the third digital signal is generated in response to the retimer determining that the first digital signal undergoes a positive voltage transition from one logic level to a higher logic level.

4383312, May 10, 1983

Nov 28, 1980

6/211011

Robert C. Reed - San Diego CA

The United States of America as represented by the Secretary of the Navy - Washington DC

G06F 1100, G01R 3128, H04B 346, H04J 314

370 13

An apparatus for testing a data multiplex transmission system by providing simulated source and sink of data for the multiplex transmission system that is compatible with the multiplex system and complies with the protocol of the Input/Output modules of the multiplex system. A programmable read only memory is programmable by means of toggle and thumbwheel switches to selectively and variably control the protocol, the length, the rate, the destination and the content of the data message. A status display is connected to the programmable read only memory to indicate the current point of progression of its programmable sequence. An error detector is connected to the programmable read only memory for determining whether the memory has stalled at a point of progression and an error display is also connected to the programmable read only memory to indicate and identify the error when this stall condition has occurred. A random access memory is included in the apparatus for storing the data received by it and a display is provided for displaying the contents of the random access memory.