ROBERT SHANNON FARRELL
Medical Practice in Portland, OR

5355467, Oct 11, 1994

Mar 8, 1994

8/208090

Peter D. MacWilliams - Aloha OR
Robert L. Farrell - Portland OR
Adalberto Golbert - Haifa, IL
Itzik Silas - Haifa, IL

Intel Corporation - Santa Clara CA

G06F 1300

395425

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

5228134, Jul 13, 1993

Jun 4, 1991

7/710075

Peter D. MacWilliams - Aloha OR
Clair C. Webb - Aloha OR
Robert L. Farrell - Portland OR

Intel Corporation - Santa Clara CA

G06F 1208, G06F 1228

395425

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cache line to be read/written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

5293603, Mar 8, 1994

Jun 4, 1991

7/710079

Peter D. MacWilliams - Aloha OR
Clair C. Webb - Aloha OR
Robert L. Farrell - Portland OR

Intel Corporation - Santa Clara CA

G06F 1208

395425

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.

4570220, Feb 11, 1986

Nov 25, 1983

6/555027

Raymond S. Tetrick - Portland OR
John Beaston - Hillsboro OR
Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Sudarshan Balachandran - Aloha OR
Edwin L. Jacks - Beaverton OR
Steven D. Kassel - Aloha OR

Intel Corporation - Santa Clara CA

G06F 1516

364200

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

4807109, Feb 21, 1989

Jan 14, 1987

7/006353

Robert L. Farrell - Portland OR
Alireza Sarabi - Hillsboro OR
Raymond S. Tetrick - Portland OR

Intel Corporation - Santa Clara CA

G06F 1340

364200

A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.