ROBERT SCOTT FRANCE, CRNA
Nursing at Hancock Dr, Austin, TX

7949851, May 24, 2011

Dec 28, 2007

11/966919

Walter Allen - Austin TX, US
Sunil Atri - Austin TX, US
Robert France - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 12/00

711203, 711202, 711E12058

Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components.

5623664, Apr 22, 1997

Jul 25, 1994

8/279605

Brian E. Calvert - Austin TX
Arthur H. Claus - Austin TX
Robert B. France - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 944

395651

A method, referred to as the interactive memory mapper or IMM (322), allows a user to program a memory (9) of a data processor (14) using a computer terminal (12) as a visual interface. The IMM allows a user to view and modify a pictorial representation of a data processor's memory space. When the IMM is utilized to allow the plurality of memory blocks to be viewed on the computer terminal, each block has visible attributes corresponding to the memory located at a memory address. Each of the plurality of memory blocks may be selected using a pointing device or keyboard and the blocks' attributes may be modified via an auxiliary controls subroutine (90) of the IMM program. The selected blocks may be created, moved, and resized to either add or subtract additional memory space, but is constrained to legal configurations determined by the specification of the data processor.

5613119, Mar 18, 1997

Jul 25, 1994

8/279602

Robert B. France - Austin TX
Arthur H. Claus - Austin TX
Brian E. Calvert - Austin TX

Motorola Inc. - Schaumburg IL

G06F 944

395651

A program (818) utilizes a functional description of a data processor to verify that the operations requested by the user are valid in the current context of the development environment (10). The program performs each of these functions by checking both physical (820) and contextual rules (838) stored in a memory (9). The program ensures that registers and memory in the data processor cannot be illegally configured and, therefore, fewer programming errors will occur during the development stages of a new data processing system.

7979667, Jul 12, 2011

Dec 10, 2007

11/953501

Walter Allen - Wellington CO, US
Robert France - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 12/10

711203, 711154, 711E12059

Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.

2012027, Oct 25, 2012

Jul 2, 2012

13/539688

Walter Allen - Wellington CO, US
Robert France - Austin TX, US

SPANSION LLC - Sunnyvale CA

G06F 12/00

711103, 711E12008

Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

7743203, Jun 22, 2010

May 11, 2007

11/747608

Robert Brent France - Austin TX, US

Spansion LLC - Sunnyvale CA

G11C 16/00, G11C 16/14, G11C 16/32, G11C 16/34

711103, 36518529, 3651853, 36518533

A memory management component can track the amount of time between erase cycles for a particular memory region, and can manage memory region such that the regions are given sufficient time to rest and recover, or are given at least as much rest time as is practical, before being subject to an erase cycle. A reclamation management component can reclaim memory region that have invalid data stored therein, and can reclaim regions on a just-in-time basis when practical, and can determine which regions to reclaim based on various factors, such as the amount of time since a region was last erased, and the number of programming errors associated with a region. The memory management component can thereby optimize the useful life, minimize or reduce loss of margin in memory regions, and minimize or reduce programming errors of memory regions, of non-volatile (e. g. , flash) memory.

8464021, Jun 11, 2013

May 28, 2008

12/127919

Walter Allen - Wellington CO, US
Sunil Atri - Austin TX, US
Robert France - Austin TX, US

Spansion LLC - Sunnyvale CA

G06F 9/34, G06F 9/26

711202, 711103, 711118, 711221

Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.