ROBERT NORMAN, M.D.
Marriage and Family Therapists at Oconnor Dr, San Jose, CA

6601191, Jul 29, 2003

Aug 18, 2000

09/641693

Robert D. Norman - San Jose CA
Christophe J. Chevallier - Palo Alto CA

Micron Technology, Inc. - Boise ID

G06C 1134

714 37, 714 42

An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be, compensated for by the memory system.

6011741, Jan 4, 2000

Jul 23, 1998

9/121348

Robert F. Wallace - Sunnyvale CA
Robert D. Norman - San Jose CA
Eliyahou Harari - Los Gatos CA

SanDisk Corporation - Sunnyvale CA

G11C 1606, G06F 1300

365221

A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

6148363, Nov 14, 2000

Apr 21, 1998

9/064528

Karl M. J. Lofgren - Newport Beach CA
Jeffrey Donald Stai - Placentia CA
Anil Gupta - Irvine CA
Robert D. Norman - San Jose CA
Sanjay Mehrotra - Milpitas CA

SanDisk Corporation - Sunnyvale CA

G06F 1200

711103

A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted.

6230233, May 8, 2001

Sep 13, 1991

7/759212

Karl M. J. Lofgren - Newport Beach CA
Robert D. Norman - San Jose CA
Gregory B. Thelin - Garden Grove CA
Anil Gupta - Irvine CA

Sandisk Corporation - Santa Clara CA

G06F 1202, G06F 1216, G06F 1210

711103

A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

5535328, Jul 9, 1996

Feb 23, 1995

8/393569

Eliyahou Harari - Los Gatos CA
Robert D. Norman - San Jose CA
Sanjay Mehrotra - Milpitas CA

SanDisk Corporation - Santa Clara CA

G06F 1200, G06F 1116

39518205

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

6212123, Apr 3, 2001

Jul 13, 1999

9/351879

Robert D. Norman - San Jose CA
Vinod C. Lakhani - Milpitas CA
Christophe J. Chevallier - Palo Alto CA

Micron Technology, Inc. - Boise ID

G11C 800

3652303

A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.

6081447, Jun 27, 2000

Mar 5, 1999

9/262813

Karl M. J. Lofgren - Newport Beach CA
Robert D. Norman - San Jose CA
Gregory B. Thelin - Garden Grove CA
Anil Gupta - Irvine CA

Western Digital Corporation - Irvine CA
SanDisk Corporation - Sunnyvale CA

G11C 1600

36518502

A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

5239213, Aug 24, 1993

Jun 11, 1992

7/897575

Robert D. Norman - San Jose CA
Sai-Keung Lee - Milpitas CA
Om Agrawal - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H03K 506

307465

A programmable logic device is disclosed having a delay line macrocell with programmably selectable taps feeding inputs to a programmable logic circuit. The delay line taps may feed the programmable logic circuit through logic circuit driving circuitry, which performs a certain amount of prepossessing on the tap signals before being provided to the programmable logic circuit. Outputs of the programmable logic circuit, which may be a programmable AND array followed by a fixed OR array, are provided to the edge-triggered inputs of dual set/reset flip flops. Other outputs of the programmable logic circuit are selectable as inputs to the delay line.

7437631, Oct 14, 2008

Aug 13, 2004

10/917870

Daniel L. Auclair - Mountain View CA, US
Jeffrey Craig - Fremont CA, US
John S. Mangan - Santa Cruz CA, US
Robert D. Norman - San Jose CA, US
Daniel C. Guterman - Fremont CA, US
Sanjay Mehrotra - Milpitas CA, US

SanDisk Corporation - Milpitas CA

G11C 29/00

714721

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

2002004, Apr 18, 2002

Oct 30, 2001

10/000155

Eliyahou Harari - Los Gatos CA, US
Robert Norman - San Jose CA, US

G06F012/00

711/103000, 711/163000, 365/185300, 365/185330

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.