ROBERT MICHAEL GLORIOSO
Pilots at Birch Hl Rd, Stow, MA

6038685, Mar 14, 2000

Sep 22, 1997

8/934747

Thomas Dale Bissett - Northborough MA
Richard D. Fiorentino - Carlisle MA
Robert M. Glorioso - Stow MA
Diane T. McCauley - Hopkinton MA
James D. McCollum - Whitinsville MA
Glenn A. Tremblay - Upton MA
Mario Troiani - Newton MA

Marathon Technologies Corporation - Stow MA

G06F 1300

714 12

In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates. In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements. Computer systems include one or more controllers and at least two computing elements.

5615403, Mar 25, 1997

Oct 2, 1995

8/537985

Thomas D. Bissett - Northborough MA
Richard D. Fiorentino - Carlisle MA
Robert M. Glorioso - Stow MA
Diane T. McCauley - Hopkinton MA
James D. McCollum - Whitinsville MA
Glenn A. Tremblay - Upton MA
Mario Troiani - Newton MA

Marathon Technologies Corporation - Boxboro MA

G06F 1300

395881

The effects of I/O race conditions caused by asynchrony between processors concurrently executing the same software and I/O devices are eliminated by executing an application program and a first associated operating system with firs processors, and executing an I/O processing program and a second associated operating system with an I/O processor. Memory requests from the application program or the first associated operating system are processed with the first processors, and memory requests from the application program to memory addresses associated with I/O devices are trapped and transmitted to the I/O processor. The I/O processor then performs the trapped memory requests with the I/O processing program after waiting for the identical request to be received from each of the first processors to eliminate the effects of race conditions caused by asynchrony between processors concurrently executing the application program or the first associated operating system and I/O devices. I/O requests may be trapped and performed by the I/O processor for the same purpose.

5600784, Feb 4, 1997

Mar 16, 1995

8/405193

Thomas D. Bissett - Northborough MA
Richard D. Fiorentino - Carlisle MA
Robert M. Glorioso - Stow MA
Diane T. McCauley - Hopkinton MA
James D. McCollum - Whitinsville MA
Glenn A. Tremblay - Upton MA

Marathon Technologies Corporation - Stow MA

G06F 1100, G01R 3128

39518210

In a first aspect, a method of synchronizing at least two computing elements that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements, monitoring the computing elements to detect the production of a selected signal by one of the computing elements, waiting for the other computing elements to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements based on the time updates. In a second aspect, fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing elements. Computer systems include one or more controllers and at least two computing elements.

5956474, Sep 21, 1999

Dec 18, 1996

8/768437

Thomas Dale Bissett - Northborough MA
Richard D. Fiorentino - Carlisle MA
Robert M. Glorioso - Stow MA
Diane T. McCauley - Hopkinton MA
James D. McCollum - Whitinsville MA
Glenn A. Tremblay - Upton MA
Mario Troiani - Newton MA

Marathon Technologies Corporation - Boxboro MA

G06F 1100

39518209

Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing element. The controllers provide input/output processings for the computing elements, as well as monitor their operations to detect errors, and control operation of the computing elements in response to the detected errors.