ROBERT MARK JAMES HENDERSON
Pilots at Ctr St, Portland, OR
License number
Oregon A5149324
Issued Date
Sep 2013
Expiration Date
Sep 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
5915 SE Center St, Portland, OR 97206
Personal information
See more information about ROBERT MARK JAMES HENDERSON at radaris.comName
Address
Phone
5121 SE Cesar E Chavez Blvd, Portland, OR 97202
5332 Harlan Dr, Klamath Falls, OR 97603
5226 Villa Dr, Klamath Falls, OR 97603
Professional information
Use Of Active Temperature Control To Provide Emmisivity Independent Wafer Temperature
US Patent:
2006000, Jan 5, 2006
Filed:
Jun 30, 2004
Appl. No.:
10/882894
Inventors:
Jack Hwang - Portland OR, US
Robert James - Portland OR, US
Eric Lambert - Beaverton OR, US
Jonathan Leonard - Vernonia OR, US
Richard Brindos - Hillsboro OR, US
Karson Knutson - Beaverton OR, US
Mark Armstrong - Portland OR, US
Justin Sandford - Tigard OR, US
Robert James - Portland OR, US
Eric Lambert - Beaverton OR, US
Jonathan Leonard - Vernonia OR, US
Richard Brindos - Hillsboro OR, US
Karson Knutson - Beaverton OR, US
Mark Armstrong - Portland OR, US
Justin Sandford - Tigard OR, US
International Classification:
G05D 23/00
US Classification:
700300000, 118724000
Abstract:
Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.
Use Of Active Temperature Control To Provide Emmisivity Independent Wafer Temperature
US Patent:
2006028, Dec 21, 2006
Filed:
Jun 16, 2005
Appl. No.:
11/156381
Inventors:
Jack Hwang - Portland OR, US
Robert James - Portland OR, US
Eric Lambert - Beaverton OR, US
Jonathan Leonard - Vernonia OR, US
Richard Brindos - Hillsboro OR, US
Karson Knutson - Beaverton OR, US
Mark Armstrong - Portland OR, US
Justin Sandford - Tigard OR, US
Robert James - Portland OR, US
Eric Lambert - Beaverton OR, US
Jonathan Leonard - Vernonia OR, US
Richard Brindos - Hillsboro OR, US
Karson Knutson - Beaverton OR, US
Mark Armstrong - Portland OR, US
Justin Sandford - Tigard OR, US
International Classification:
H01L 21/306, G01R 31/00, H01L 21/461
US Classification:
438715000, 216059000, 216060000, 156345240
Abstract:
Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.
Method For Forming Superactive Deactivation-Resistant Junction With Laser Anneal And Multiple Implants
US Patent:
2013026, Oct 10, 2013
Filed:
Dec 9, 2011
Appl. No.:
13/995171
Inventors:
Jacob M. Jensen - Beaverton OR, US
Harold W. Kennel - Portland OR, US
Tahir Ghani - Portland OR, US
Robert D. James - Portland OR, US
Mark Y. Liu - West Linn OR, US
Harold W. Kennel - Portland OR, US
Tahir Ghani - Portland OR, US
Robert D. James - Portland OR, US
Mark Y. Liu - West Linn OR, US
International Classification:
H01L 21/268
US Classification:
438530
Abstract:
A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant.
Pulsed Laser Anneal Process For Transistors With Partial Melt Of A Raised Source-Drain
US Patent:
2013028, Oct 31, 2013
Filed:
Dec 19, 2011
Appl. No.:
13/976822
Inventors:
Jacob Jensen - Beaverton OR, US
Tahir Ghani - Portland OR, US
Mark J. Liu - West Linn OR, US
Harold Kennel - Portland OR, US
Robert James - Portland OR, US
Tahir Ghani - Portland OR, US
Mark J. Liu - West Linn OR, US
Harold Kennel - Portland OR, US
Robert James - Portland OR, US
International Classification:
H01L 29/66, H01L 29/78
US Classification:
257288, 438293
Abstract:
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.
Selective Laser Annealing Process For Buried Regions In A Mos Device
US Patent:
2013028, Oct 31, 2013
Filed:
Dec 19, 2011
Appl. No.:
13/976831
Inventors:
Jacob Jensen - Beaverton OR, US
Tahir Ghani - Portland OR, US
Mark Y. Liu - West Linn OR, US
Harold Kennel - Portland OR, US
Robert James - Portland OR, US
Tahir Ghani - Portland OR, US
Mark Y. Liu - West Linn OR, US
Harold Kennel - Portland OR, US
Robert James - Portland OR, US
International Classification:
H01L 29/66
US Classification:
438197
Abstract:
Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.
Area Scaling On Trigate Transistors
US Patent:
2013032, Dec 5, 2013
Filed:
Jun 1, 2012
Appl. No.:
13/487111
Inventors:
Abhijit Jayant Pethe - Hillsboro OR, US
Justin S. Sandford - Tigard OR, US
Christopher J. Wiegand - Portland OR, US
Robert D. James - Portland OR, US
Justin S. Sandford - Tigard OR, US
Christopher J. Wiegand - Portland OR, US
Robert D. James - Portland OR, US
International Classification:
H01L 21/336, H01L 27/088
US Classification:
257368, 438299, 257E21409, 257E2706
Abstract:
Improving an area scaling on tri-gate transistors is described. An insulating layer is deposited on a fin on a substrate. The insulating layer is recessed to expose the fin. The corner of the fin is rounded off using a noble gas. A gate dielectric layer is deposited on the rounded corner. The radius of curvature of the corner is controllable by adjusting a bias power to the substrate. The radius of curvature of the corner is determined based on the width of the fin to reduce an area scaling of the array.
Apparatus And Method Of Backside Anneal For Reduced Topside Pattern Effect
US Patent:
2008007, Mar 27, 2008
Filed:
Sep 22, 2006
Appl. No.:
11/525770
Inventors:
Karson L. Knutson - Beaverton OR, US
Robert James - Portland OR, US
Robert James - Portland OR, US
International Classification:
H01L 21/336
US Classification:
438308
Abstract:
Embodiments of an apparatus and methods for heating an absorbing layer on a wafer by exposing the wafer to an electromagnetic energy source are generally described herein. Other embodiments may be described and claimed.