MR. ROBERT LEE MARTIN, MD
Medical Practice at Forest Ln, Dallas, TX

4536664, Aug 20, 1985

Feb 16, 1983

6/467105

Robert C. Martin - Dallas TX

Texas Instruments Incorporated - Dallas TX

H03K 19092, H03K 19084, H03K 19013

307475

A high speed, noninverting circuit for providing an interface between transistor-transistor logic gates and Schottky transistor logic gates. In one embodiment the output of a TTL circuit is coupled through a Schottky diode to an emitter-follower whose input is Schottky clamped. The output of the emitter-follower is coupled to a constant current sink and to the cathode of a low barrier Schottky diode, the anode of which forms the STL-compatible output of the interface circuit. The present circuit thus performs a noninverting level translation with minimum propagation delay.

5612632, Mar 18, 1997

Nov 29, 1994

8/346562

Shivaling Mahant-Shetti - Los Angeles CA
Kevin Ovens - Plano TX
Clive Bittlestone - Allen TX
Robert C. Martin - Dallas TX
Robert J. Landers - Plano TX

Texas Instruments Incorporated - Dallas TX

H03K 19173, H03K 1900

326 46

A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal.

3999080, Dec 21, 1976

Dec 23, 1974

5/535405

Scott Weathersby - Houston TX
Earl C. Wilson - Houston TX
Benjamin J. Sloan - Richardson TX
Robert C. Martin - Dallas TX

Texas Instruments Inc. - Dallas TX

H03K 1908, H03K 1922, H03K 1936

307203

A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1. 6 volts centered on a circuit threshold of 1. 6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2. 0 volts at 25. degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F. sub.