Robert L. Davis, JR
Architects at College Ave, Fort Collins, CO
License number
Colorado 201777
Issued Date
Aug 27, 1982
Renew Date
Feb 12, 2016
Expiration Date
Oct 31, 2017
Type
Architect
Address
Address
141 S College Ave STE 102, Fort Collins, CO 80524
Professional information
Method And Apparatus For Indentifying Causes Of Poor Silicon-To-Simulation Correlation
US Patent:
6493851, Dec 10, 2002
Filed:
May 3, 2001
Appl. No.:
09/848489
Inventors:
Randall E. Bach - Stillwater MN
Robert W. Davis - Fort Collins CO
Robert W. Davis - Fort Collins CO
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1750
US Classification:
716 4, 716 6
Abstract:
A method identifies the cause of poor correlation between an integrated circuit model and measured integrated circuit performance. The method includes determining the propagation delays through two separate integrated circuit components. The propagation delays are then compared to each other to identify the cause of the poor correlation.
Method Of Delay Calculation For Variation In Interconnect Metal Process
US Patent:
6880142, Apr 12, 2005
Filed:
Oct 16, 2002
Appl. No.:
10/272182
Inventors:
Qian Cui - Cupertino CA, US
Robert W. Davis - Fort Collins CO, US
Sandeep Bhutani - Sunnyvale CA, US
Payman Zarkesh-Ha - Fremont CA, US
Prabhakaran Krishnamurthy - San Jose CA, US
Robert W. Davis - Fort Collins CO, US
Sandeep Bhutani - Sunnyvale CA, US
Payman Zarkesh-Ha - Fremont CA, US
Prabhakaran Krishnamurthy - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F009/45, G06F017/50
US Classification:
716 6, 716 4, 703 19
Abstract:
A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.
Bent Gate Transistor Modeling
US Patent:
6871333, Mar 22, 2005
Filed:
Oct 7, 2002
Appl. No.:
10/265803
Inventors:
SangJune Park - Colorado Springs CO, US
Robert W. Davis - Fort Collins CO, US
Robert W. Davis - Fort Collins CO, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F009/45
US Classification:
716 5, 716 4, 716 6
Abstract:
A method of characterizing a total width and an overall effective length for a bent gate. The bent gate is divided into logical portions, and each of the logical portions is designated as one of a bent portion, a corner portion, and a straight portion. A corner portion gate width and a corner portion effective length are computed for each of the logical portions designated as a corner portion. Similarly, a bent portion gate width and a bent portion effective length are computed for each of the logical portions designated as a bent portion. Likewise, a straight portion gate width and a straight portion effective length are computed for each of the logical portions designated as a straight portion. The total width of the bent gate is computed from the corner portion gate width, the bent portion gate width, and the straight portion gate width. Similarly, the overall effective length of the bent gate is computed from the corner portion effective length, the bent portion effective length, and the straight portion effective length.