ROBERT KEITH BARNES
Pilots at Stonehenge Dr, Fort Collins, CO

7280002, Oct 9, 2007

Mar 3, 2005

11/070985

Alvin Leng Sun Loke - Fort Collins CO, US
Tin Tin Wee - Fort Collins CO, US
Robert Keith Barnes - Fort Collins CO, US
Kari Lee Arave - Fort Collins CO, US
Thomas Edward Cynkar - Fort Collins CO, US
James Ruhl Pfiester - Fort Collins CO, US

Avago Technologies General IP Pte Ltd - Singapore

H03B 5/12

331177V, 331 36 C

A method and apparatus is presented for generating a reference voltage that biases a metal-oxide-semiconductor (MOS) transistor used as a varactor in capacitive tuning applications. In one embodiment, a biasing circuit is implemented. The biasing circuit comprises a diode-clamped FET and an element coupled to the diode-clamped FET at a connection point. The element produces a constant current through the diode-clamped FET. A voltage is produced at the connection point. The voltage is one gate overdrive plus a threshold voltage above ground or one gate overdrive plus a threshold voltage below VDD. Establishing a threshold voltage in this way enables the biasing circuit to track an ideal voltage of a varactor that is coupled to the biasing circuit through the threshold voltage.

7277518, Oct 2, 2007

Nov 20, 2003

10/717778

Alvin Leng Sun Loke - Fort Collins CO, US
James Oliver Barnes - Fort Collins CO, US
Robert Keith Barnes - Fort Collins CO, US
Michael M. Oshima - Los Altos CA, US
Ronald Ray Kennedy - Fort Collins CO, US
Charles E. Moore - Loveland CO, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

H03D 3/24

375373, 375374, 375376, 327148, 327157, 331 17

A phase-locked loop includes a voltage-controlled oscillator and a charge-pump loop filter. The voltage-controlled oscillator includes a varactor having a first set of capacitor cells configured to adjust a capacitance based on a first control voltage, and a second set of capacitor cells configured to adjust a capacitance based on a second control voltage. The charge-pump loop filter receives a first and a second update signal, each having at least one state based on a phase difference between a first clock and a second clock, and comprises a first component and a second component. The first component is configured to adjust, during an update period, a voltage across an impedance from a reference level based on the states of the first and second update signals and to return the voltage across the impedance to the reference level prior to an end of the update period, wherein the voltage across the impedance comprises the first control voltage. The second component is configured to adjust a voltage across a capacitor based on the states of the first and second input signals, wherein the voltage across the capacitor comprises the second control voltage.

7274764, Sep 25, 2007

Nov 20, 2003

10/718206

Alvin Leng Sun Loke - Fort Collins CO, US
Robert Keith Barnes - Fort Collins CO, US
James Oliver Barnes - Fort Collins CO, US

Avago Technologies General IP (Singapore) Pte. Ltd - Singapore

H03D 3/24

375373, 375374, 375376, 327148, 327157

In one embodiment, the present invention provides a phase-locked loop comprising a charge-pump loop filter and a phase detector system. The charge-pump loop filter is configured to provide a control voltage having a voltage level based on a state of a first control signal and on a state of a second control signal. The phase detector system is configured to receive a first clock, a second clock, and a control signal defining a plurality of states including a first state and a second state. The phase detector system is further configured to provide the first control signal and the second control signal each having a state based on a phase difference between the first and second clocks when the control signal has the first state, and to provide the first control signal and second control signal each having a state asynchronously controlled by the control signal when the control signal has the second state.

8634503, Jan 21, 2014

Mar 31, 2011

13/076640

Brian J. Misek - Fort Collins CO, US
Robert K. Barnes - Fort Collins CO, US
Peter J. Meier - Fort Collins CO, US

H04L 27/00

375326, 375316, 375354, 375373, 375376, 375375, 327141, 327144, 327146, 327147, 327155, 327156

A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

8432191, Apr 30, 2013

Jan 24, 2011

13/011989

Robert Keith Barnes - Fort Collins CO, US

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

G01R 25/00, H03D 13/00

327 3, 327 2, 327 12

A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.

2013025, Oct 3, 2013

Apr 2, 2012

13/437662

Robert Thelen - Fort Collins CO, US
Michael Farmer - Fort Collins CO, US
Robert K. Barnes - Fort Collins CO, US

Avago Technologies Enterprise IP (Singapore) Pte. Ltd. - Singapore

H03L 7/08

327158, 327156

In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

6975176, Dec 13, 2005

Nov 20, 2003

10/717834

Alvin Leng Sun Loke - Fort Collins CO, US
Robert Keith Barnes - Fort Collins CO, US

Agilent Technologies, Inc. - Palo Alto CA

H03B005/00, H03L007/99

331177V, 331 14, 331 17, 331 18, 331 36 C, 331 2

In one embodiment, the present invention provides a system including a varactor and a voltage generator. The varactor includes a set of substantially equal voltage-tunable capacitor cells, each having a capacitive range that varies with a first plurality of operating parameters and each providing a capacitance within the range based on a voltage level of a reference voltage. The voltage generator is configured to provide the reference voltage, wherein the voltage level of the reference voltage corresponds to a desired capacitance within the capacitive range and varies based on a second plurality of operating parameters which are substantially the same as the first plurality of operating parameters, and wherein the voltage level of the reference voltage causes each capacitor cell to provide the desired capacitance.