ROBERT ERNEST TRZCINSKI
Pilots at Ctr Rd, Rhinebeck, NY

7939910, May 10, 2011

Aug 6, 2010

12/851814

Choongyeun Cho - Hopewell Junction NY, US
Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01L 29/00

257532, 257306, 257307, 257528, 257E29343, 438381

Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

2013019, Jul 25, 2013

Apr 12, 2011

13/640588

Daniel Patrick Connors - Pleasant Valley NY, US
Jerome Felsenstein - Ossining NY, US
Robert E. Trzcinski - Rhinebeck NY, US
James J. Wynne - Mt. Kisco NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

A61B 18/20

606 17

Disclosed is an improved system and method for efficiently removing tissue using laser ablation. A first laser emits a first laser beam with a variable first integrated fluence sufficient to ablate tissue. The first laser beam is movably positioned over one or more surfaces of the tissue and the first integrated fluence varies over different levels with position, so different thicknesses of tissue are ablated at different surface positions in order to modify the contour of the surface of the tissue. Modifications include tissue smoothing, removing, feathering, sharpening, and roughening. In one preferred embodiment the tissue is eschar that is removed, unveiling viable tissue. In alternate preferred embodiments, one or more additional lasers beams with different wavelengths, with integrated fluence sufficient to ablate tissue, are moved over the surface of the tissue until a second ablation reaches a second self-termination point, e.g., determined by affects of chemicals below the termination point that absorb the second laser beam without producing the temperature increase necessary for ablation to continue.

8419895, Apr 16, 2013

May 27, 2010

12/788843

Bing Dang - Chappaqua NY, US
John Knickerbocker - Yorktown Heights NY, US
Aparna Prabhakar - North White Plains NY, US
Peter Sorce - Poughkeepsie NY, US
Robert E. Trzcinski - Rhinebeck NY, US
Cornelia K. Tsang - Mohegan Lake NY, US

International Business Machines Corporation - Armonk NY

B32B 38/10

156703, 156712, 156753, 156930, 438976

A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

8227891, Jul 24, 2012

Jan 30, 2009

12/362877

Choongyeun Cho - Beacon NY, US
Daeik Kim - Fishkill NY, US
Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00

257531, 716107, 716 9

Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

2012022, Sep 6, 2012

May 11, 2012

13/469464

Choongyeun Cho - Beacon NY, US
Daeik Kim - Fishkill NY, US
Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01L 29/86, H01L 21/02

257531, 438381, 257E29325, 257E21022

Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

8388782, Mar 5, 2013

May 27, 2010

12/788832

Paul S. Andry - Yorktown Heights NY, US
Bing Dang - Chappaqua NY, US
John Knickerbocker - Yorktown Heights NY, US
Peter J. Sorce - Poughkeepsie NY, US
Robert E. Trzcinski - Rhinebeck NY, US
Cornelia K. Tsang - Mohegan Lake NY, US

International Business Machines Corporation - Armonk NY

B32B 38/10, B32B 37/12

156 64, 156247, 156712, 156930, 438 14

A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C. ; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C. ; and a handler adhered to the wafer using the layer of adhesive.

2011029, Dec 1, 2011

May 27, 2010

12/788839

Bing Dang - Chappaqua NY, US
Matthew Farinelli - Bronx NY, US
John Knickerbocker - Yorktown Heights NY, US
Aparna Prabhakar - North White Plains NY, US
Robert E. Trzcinski - Rhinebeck NY, US
Cornelia K. Tsang - Mohegan Lake NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

B32B 38/10, B29C 65/16

156247, 1563796

A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.

7518850, Apr 14, 2009

May 18, 2006

11/436248

Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01G 4/38, H01G 4/00, H01L 27/108, H01L 29/94, H01L 21/20

361328, 257303, 257307, 257595, 361329, 3613012, 438396

A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

2008007, Apr 3, 2008

Sep 29, 2006

11/536896

Choongyeun Cho - Beacon NY, US
Daeik Kim - Fishkill NY, US
Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01L 29/00

257531

Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

7579644, Aug 25, 2009

May 18, 2006

11/436249

Jonghae Kim - Fishkill NY, US
Moon J. Kim - Wappingers Falls NY, US
Jean-Olivier Plouchart - New York NY, US
Robert E. Trzcinski - Rhinebeck NY, US

International Business Machines Corporation - Armonk NY

H01L 29/94

257312, 257595, 257E29344

One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.