ROBERT EMMETT AYERS
Physical Therapy in Durham, NC
License number
Pennsylvania PT002170L
Category
Physical Therapy
Type
Physical Therapist
Address
Address
2
Durham, NC 27703
Pennsylvania
Pennsylvania
Personal information
See more information about ROBERT EMMETT AYERS at radaris.comName
Address
Phone
516 Friel Rd, Baden, PA 15005
51 Circle Dr, Delmont, PA 15626
4903 Forest Oaks Dr, Greensboro, NC 27406
494 Bendersville Wenksvill Rd, Aspers, PA 17304
530 Middle Ave, Wilmerding, PA 15148
Professional information
Robust Power Plane Configuration In Printed Circuit Boards
US Patent:
8576578, Nov 5, 2013
Filed:
Jun 27, 2011
Appl. No.:
13/170010
Inventors:
Robert L. Ayers - Durham NC, US
Michael L. Scollard - Raleigh NC, US
Heidi D. Williams - Cary NC, US
Michael L. Scollard - Raleigh NC, US
Heidi D. Williams - Cary NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 1/11, H05K 1/14
US Classification:
361794, 361748, 361799, 36167902
Abstract:
A robust printed circuit board (PCB) that includes at least two power layers that are used in providing power to components connected to the PCB. The power layers may be a power plane layer and a ground plane layer. The power plane layer is situated such that its edge is pulled back a second distance from the planar edge of the PCB. The ground plane layer is situated such that its edge is pulled back a first distance from the planar edge of the PCB. The second distance and the first distance are different, and as a result, the planar edges of the power plane layer and the ground plane layer respectively do not coincide.
Boundary Scan Apparatus And Interconnect Test Method
US Patent:
2004008, Apr 29, 2004
Filed:
Oct 29, 2002
Appl. No.:
10/282825
Inventors:
Robert Ayers - Durham NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R031/28
US Classification:
714/727000
Abstract:
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.
Boundary Scan Apparatus And Interconnect Test Method
US Patent:
2006015, Jul 13, 2006
Filed:
Jan 19, 2006
Appl. No.:
11/337045
Inventors:
Robert Ayers - Durham NC, US
International Classification:
G01R 31/28
US Classification:
714727000
Abstract:
An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for boundary scan testing is segregated from the operational signal path which is used when the device is performing its normal function.
Method And Apparatus For Testing Quiescent Current In Integrated Circuits
US Patent:
5760598, Jun 2, 1998
Filed:
Feb 12, 1996
Appl. No.:
8/599900
Inventors:
Robert Lee Ayers - Durham NC
Geoffrey B. Stephens - Cary NC
Geoffrey B. Stephens - Cary NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3126
US Classification:
324765
Abstract:
A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.
Method And Apparatus For Testing Quiescent Current In Integrated Circuits
US Patent:
5939897, Aug 17, 1999
Filed:
Feb 11, 1998
Appl. No.:
9/022305
Inventors:
Robert Lee Ayers - Durham NC
Geoffrey B. Stephens - Cary NC
Geoffrey B. Stephens - Cary NC
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 190948, H03K 1900
US Classification:
326 58
Abstract:
A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.