ROBERT EDWARD WALKER
Medical Practice in Menlo Park, CA
License number
Pennsylvania MD039318E
Category
Medicine
Type
Medical Physician and Surgeon
Address
Address
2
Menlo Park, CA 94025
Pennsylvania
Pennsylvania
Personal information
See more information about ROBERT EDWARD WALKER at radaris.comName
Address
Phone
5043 Shalimar Cir, Fremont, CA 94555
5031 Cherrywood Dr, Oceanside, CA 92056
5026 Veloz Ave, Tarzana, CA 91356
506 Florence Dr, Vacaville, CA 95688
505 S 4Th St, Clearfield, PA 16830
Professional information
Testing Of Integrated Circuits Using Clock Bursts
US Patent:
5177440, Jan 5, 1993
Filed:
Jul 11, 1991
Appl. No.:
7/714962
Inventors:
Robert M. Walker - Atherton CA
Dick L. Liu - Saratoga CA
Dick L. Liu - Saratoga CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R 3128
US Classification:
324158R
Abstract:
A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.
Testing Of Integrated Circuits Using Clock Bursts
US Patent:
5049814, Sep 17, 1991
Filed:
Dec 27, 1989
Appl. No.:
7/457910
Inventors:
Robert M. Walker - Atherton CA
Dick L. Liu - Saratoga CA
Dick L. Liu - Saratoga CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R 3128
US Classification:
324158R
Abstract:
A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.
High-Speed Cmos Buffer With Controlled Slew Rate
US Patent:
4987324, Jan 22, 1991
Filed:
Aug 27, 1987
Appl. No.:
7/090273
Inventors:
Anthony Y. Wong - Cupertino CA
Robert M. Walker - Atherton CA
Robert M. Walker - Atherton CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03K 19094, H03K 1716, H03K 301, H03K 17687
US Classification:
307451
Abstract:
A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.