Robert E Miller
Veterinary in Loveland, CO

5224208, Jun 29, 1993

Mar 16, 1990

7/494708

Robert H. Miller - Loveland CO
Roger W. Swanson - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1572

395125

A method and apparatus for performing the majority of texture map gradient calculations once per polygon so as to increase processing speed in a graphics system. Texture values are identified for each vertex of an input polygon and are interpolated over the polygon in perspective space in order to find the corresponding values at a given pixel within the polygon. The perspective values of the vertices are linearly interpolated across the polygon to determine the value at the given pixel. The texture gradients are then calculated by defining vectors perpendicular and parallel to the horizon of the plane containing the input polygon so that the resulting components may be calculated. The resulting value is the texture gradient, which may then be used to address a texture map to determine the pre-filtered texture value for that point. A hardware implementation performs the necessary calculations for each pixel in the input polygon.

5390134, Feb 14, 1995

Jan 29, 1993

8/011447

Craig Heikes - Ft. Collins CO
Robert H. Miller - Loveland CO

Hewlett-Packard Company - Palo Alto CA

G06F 750

364745

A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.

6298368, Oct 2, 2001

Apr 23, 1999

9/299196

Robert H Miller - Loveland CO

Agilent Technologies, Inc. - Palo Alto CA

G06F 738

708606

A bit position, M, that determines the accuracy and efficiency of the approximation is selected from an N bit binary number. The multiplicand is generated by removing the Mth bit from the binary number, shifting the bits of lower order than the Mth bit up on position, then filling the lowest order bit with a zero. The multiplier is generated by removing the Mth bit, and all lower order bits from the binary number. Booth's algorithm is then used to multiply the multiplicand and the multiplier except that the Mth bit is used instead of an assumed zero during the first step of the multiplication. In hardware, a partial Booth-encoded multiplier is used to produce and approximate square of a binary number. For an N bit number, and a selected bit in the Mth position, the partial Booth-encoded multiplier has N columns, and N-M rows and N-M booth encoders. The inputs to the columns are wired so that the multiplicand has the Mth bit from the binary number removed and the bits of lower order than the Mth bit up are shifted up position, the lowest order bit being filled with a zero.

5798952, Aug 25, 1998

Feb 29, 1996

8/608798

Robert H. Miller - Loveland CO
Rudolfo G. Beraha - Los Altos CA

Hewlett-Packard Company - Palo Alto CA

G06F 700, G06F 738, G06F 750

3647151

Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position. The raw sum is normalized by shifting it left by J-many bit positions and adjusting its exponent by J.

5317204, May 31, 1994

May 19, 1992

7/885797

Jeffry D. Yetter - Ft. Collins CO
Robert H. Miller - Loveland CO

Hewlett-Packard Company - Palo Alto CA

H03K 19017

307443

The adverse effects of charge sharing in dynamic logic gates are mitigated. The dynamic logic gates have an inverting buffer for providing a gate output, an arming mechanism for precharging the inverting buffer input, and ladder logic for receiving a gate input and for discharging the inverting buffer input to ground. The ladder logic comprises a plurality of transistors connected in ladder-like manner. In a first embodiment, the interstitial space between parallel transistor gates in the ladder logic is reduced so as to minimize parasitic capacitances. In a second embodiment, the parasitic capacitance of at a converging node defined by at least three converging transistors is minimized by disposing the transistor gates adjacent one another so that the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates. In a third embodiment, a precharger is disposed to inject charge at the converging node when the inverting buffer input is precharged by the arming mechanism. Finally, in a fourth embodiment, the plurality of transistors in the ladder logic are connected in a ladder-like manner exclusively to thereby define a plurality of mutually exclusive paths to ground.

5434520, Jul 18, 1995

May 19, 1992

7/885800

Jeffry D. Yetter - Fort Collins CO
Robert H. Miller - Loveland CO

Hewlett-Packard Company - Palo Alto CA

H03K 1900

326 93

Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.

5706323, Jan 6, 1998

Mar 1, 1996

8/609305

Robert H. Miller - Loveland CO

Hewlett-Packard Company - Palo Alto CA

G11C 1900

377 73

A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2. sup. N signal lines being asserted. Simultaneous assertion of more than one of the 2. sup. N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2. sup. N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2. sup. N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2. sup.

2006018, Aug 17, 2006

Feb 16, 2005

11/058767

Robert Miller - Loveland CO, US

H03K 23/00

327115000

A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other memory element outputs and provides an input to the closed loop system to generate a self-initializing state machine.

5740181, Apr 14, 1998

Jun 12, 1996

8/662403

Craig A. Heikes - Fort Collins CO
Glenn T. Colon-Bonet - Fort Collins CO
David R. Smentek - Columbia MD
Robert H. Miller - Loveland CO

Hewlett-Packard Co. - Palo Alto CA

G06F 1100

371 223

The operation of a pipeline is observed by launching two or more sets of data into the pipeline on consecutive clock cycles. The clock free-runs for as many cycles as it takes the data to propagate through the stages of the pipeline. The output latches of each stage of the pipeline are only sampled when the data of interest is held in each output latch, respectively. Observation may be completely controlled through a standard test access port (TAP). Observation may be accomplished by halting the clock to scan new data in and results out, or with the clock free-running. The inputs to the pipeline may come from test registers or from circuitry which feeds the pipeline during normal operation.

2008020, Aug 28, 2008

Feb 22, 2007

11/677902

Robert Harry Miller - Loveland CO, US
Gilbert Yoh - Fort Collins CO, US
Robert J. Martin - Timnath CO, US

H03K 19/0948

326121

An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2possible output combinations, where the n outputs assume a state that is a subset of the 2possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2possible output combinations.