ROBERT E MILLER
Broker in Braintree, MA

4383295, May 10, 1983

Feb 9, 1979

6/011001

Robert C. Miller - Braintree MA
John J. Bradley - Framingham MA
Boyd E. Darden - Concord MA
Ming T. Miu - Chelmsford MA
Theodore R. Staplin - Chelmsford MA

Honeywell Information Systems Inc. - Waltham MA

G06F 906

364200

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character.

4300193, Nov 10, 1981

Jan 31, 1979

6/008003

John J. Bradley - Framingham MA
Robert C. Miller - Braintree MA
Ming T. Miu - Chelmsford MA
Theodore R. Staplin - Chelmsford MA

Honeywell Information Systems Inc. - Waltham MA

G06F 300

364200

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

4375638, Mar 1, 1983

Jun 16, 1980

6/159719

David B. O'Keefe - Westford MA
Robert C. Miller - Braintree MA

Honeywell Information Systems Inc. - Waltham MA

G09G 116

340726

A refresh memory address generation apparatus for a video display controller is disclosed wherein rows of character information stored in a display refresh memory may be relocated without requiring the reconstruction of the display information as stored in the display refresh memory. A roll register and PROMs precoded to perform modular addition and multiplication are used to generate an address used to access the display controller refresh memory such that all but one stationary row of information on the display screen may be scrolled (rolled) up. The scrolling of the information on the display screen is accomplished without requiring movement of the display information in the refresh memory, and the only rewrite of information in the refresh memory is done to blank the one row of information which is vacated.

4321665, Mar 23, 1982

Jan 31, 1979

6/008121

John J. Bradley - Framingham MA
Richard L. King - Hollis NH
Robert C. Miller - Braintree MA
Ming T. Miu - Chelmsford MA
Theodore R. Staplin - Chelmsford MA

Honeywell Information Systems Inc. - Waltham MA

G06F 300

364200

In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

4293908, Oct 6, 1981

Jan 31, 1979

6/008001

John J. Bradley - Framingham MA
Thomas O. Holtey - Newton Lower Falls MA
Robert C. Miller - Braintree MA
Ming T. Miu - Chelmsford MA
Theodore R. Staplin - Chelmsford MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1300

364200

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

5148533, Sep 15, 1992

Jan 5, 1989

7/294534

Thomas F. Joyce - Westford MA
Robert C. Miller - Braintree MA
Marc C. Vogt - Nashua NH

Bull HN Information Systems Inc. - Billerica MA

G06F 1212

395425

In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit.

4292668, Sep 29, 1981

Jan 31, 1979

6/008002

Robert C. Miller - Braintree MA
John J. Bradley - Framingham MA
Richard L. King - Hollis NH
Ming T. Miu - Chelmsford MA
Theodore R. Staplin - Chelmsford MA

Honeywell Information Systems Inc. - Waltham MA

G06F 300

364200

In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

4312068, Jan 19, 1982

Mar 7, 1978

5/884465

Gary J. Goss - Acton MA
Robert C. Miller - Braintree MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1110

371 37

A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

4727486, Feb 23, 1988

May 2, 1986

6/858786

Michael D. Smith - Winchester MA
Llewelyn S. Dunwell - Lynn MA
Richard A. Lemay - Carlisle MA
Robert C. Miller - Braintree MA
Theodore R. Staplin - Chelmsford MA
William E. Woods - Natick MA
John L. Curley - North Andover MA

Honeywell Information Systems Inc. - Waltham MA

G06F 900, G06F 922, G06F 930

364200

A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

4419727, Dec 6, 1983

Jun 1, 1981

6/269502

Thomas O. Holtey - Newton MA
Robert C. Miller - Braintree MA

Honeywell Information Systems Inc. - Waltham MA

G06F 936

364200

A paging apparatus for improved mapping of virtual addresses to real addresses, addressing physical devices coupled to various communication buses, and controlling flow of data. By means of an eight-bit addressing apparatus activated for certain instructions which normally can address only 256 locations, an additional 512 locations can typically be addressed by generating control signals to modify a virtual address into a real address capable of addressing the additional locations. Additionally, the apparatus can control flow of data by enabling or disabling data control apparatus.