Robert Dixon
Electrician at Collyer St, Longmont, CO
License number
Colorado 32091
Issued Date
Aug 12, 2004
Renew Date
Aug 12, 2004
Type
Electrical Apprentice
Address
Address
1113 Collyer St, Longmont, CO 80501
Professional information
Device-Managed Host Buffer
US Patent:
6981123, Dec 27, 2005
Filed:
May 22, 2003
Appl. No.:
10/443947
Inventors:
Robert W. Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F012/08
US Classification:
711203, 711113, 711122
Abstract:
A method and apparatus is provided to virtually increase the size of the memory cache of a peripheral device without additional cost. A portion of the memory space of a host computer is used as additional cache memory for the peripheral device. The peripheral device and the host computer may be interfaced with an interface that has a first-party direct memory access (FPDMA) mechanism, for example, IEEE 1394 or Serial ATA. FPDMA allows the peripheral device to access the memory space of the host computer under the control of the peripheral device. The host computer provides the peripheral device with the location of the additional cache memory. The peripheral device can transfer data to and from the additional cache memory via FPDMA. The peripheral device effectively manages the additional cache memory as part of the peripheral device's own cache.
Device-Managed Host Buffer
US Patent:
2006011, May 25, 2006
Filed:
Nov 2, 2005
Appl. No.:
11/265617
Inventors:
Robert Dixon - Longmont CO, US
International Classification:
G06F 12/00
US Classification:
711170000, 711114000, 710022000
Abstract:
A method and apparatus is provided to virtually increase the size of the memory cache of a peripheral device without additional cost. A portion of the memory space of a host computer is used as additional cache memory for the peripheral device. The peripheral device and the host computer may be interfaced with an interface that has a first-party direct memory access (FPDMA) mechanism, for example, IEEE or Serial ATA. FPDMA allows the peripheral device to access the memory space of the host computer under the control of the peripheral device. The host computer provides the peripheral device with the location of the additional cache memory. The peripheral device can transfer data to and from the additional cache memory via FPDMA. The peripheral device effectively manages the additional cache memory as part of the peripheral device's own cache.
Dynamic Data Flow Management In A Multiple Cache Architecture
US Patent:
8463984, Jun 11, 2013
Filed:
Dec 31, 2009
Appl. No.:
12/650657
Inventors:
Edwin Scott Olds - Fort Collins CO, US
Timothy Richard Feldman - Louisville CO, US
David Warren Wheelock - Longmont CO, US
Steven Scott William - Longmont CO, US
Robert William Dixon - Longmont CO, US
Timothy Richard Feldman - Louisville CO, US
David Warren Wheelock - Longmont CO, US
Steven Scott William - Longmont CO, US
Robert William Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 12/00
US Classification:
711103, 711158
Abstract:
The disclosure is related to systems and methods of dynamic dataflow in a multiple cache architecture. In an embodiment, a system having a data storage device with a multiple cache architecture may detect at least one attribute affecting a data storage workload or data storage performance. The system may select at least one of a plurality of data flow schemes based on the at least one attribute, which may be done to optimize the data storage workload for various conditions. In another embodiment, a data storage controller may automatically and dynamically select one of multiple data flow schemes within a data storage device having a multiple cache architecture. The data storage controller may monitor attributes to determine which data flow scheme to select for various workloads of the data storage device.
Dynamic Buffer Size Allocation For Multiplexed Streaming
US Patent:
6993604, Jan 31, 2006
Filed:
Jun 27, 2001
Appl. No.:
09/894518
Inventors:
Robert William Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 3/00
US Classification:
710 56, 710 53, 710 54, 710 55, 710 57
Abstract:
A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.
Data Storage System With Non-Volatile Memory For Error Correction
US Patent:
8255774, Aug 28, 2012
Filed:
Feb 17, 2009
Appl. No.:
12/372314
Inventors:
Robert William Dixon - Longmont CO, US
Assignee:
Seagate Technology - Cupertino CA
International Classification:
G11C 29/00
US Classification:
714773
Abstract:
The present disclosure provides a data storage system with non-volatile memory for error correction. In one example, a data storage system is provided and includes a first data storage device comprising a first non-volatile data storage medium and a second data storage device that comprises a second non-volatile data storage medium. The system also includes a controller configured to store data to the first data storage device. The controller is configured to selectively generate error correction information for selected portions of the data based on at least one attribute associated with the data and store the error correction information in the second data storage device.
Interface Bus Optimization For Overlapping Write Data
US Patent:
7076593, Jul 11, 2006
Filed:
Dec 9, 2003
Appl. No.:
10/731285
Inventors:
Robert W. Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 13/36
US Classification:
710310, 710 39, 710305, 710107
Abstract:
Embodiments of the present invention are devices with a queue for receiving a plurality of data write requests and having a means for comparing the data write requests in the queue and then requesting only data identified by the data write requests that would not be overwritten by any later received data write requests in the queue. By requesting only the data that is not overwritten by subsequent data write requests, the data actually transferred over the bus is minimized given the current queue of data write requests. One aspect of the present invention includes a method of requesting data from a host over a data bus.
Method And System For Cache Management Algorithm Selection
US Patent:
6883066, Apr 19, 2005
Filed:
Dec 11, 2001
Appl. No.:
10/014371
Inventors:
James Arthur Herbst - Longmont CO, US
Carol Michiko Baum - Longmont CO, US
Robert William Dixon - Longmont CO, US
Carol Michiko Baum - Longmont CO, US
Robert William Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F012/00
US Classification:
711118, 711117, 711129, 711133, 711134
Abstract:
In a data storage device, a system of method of optimizing cache management. A method includes selecting a set of cache management algorithms associated with a predetermined pattern in a sequence of commands. Statistics based on a sequence of commands are gathered and a pattern is detected from the statistics. The pattern is associated with predetermined known patterns to identify a set of cache management algorithms that are optimized for the known pattern. A system includes usage statistics that are correlated among a set of known usage patterns. A switch chooses the set of cache management algorithms associated with the known pattern that most closely matches the usage statistics.
Systems And Methods Of Tiered Caching
US Patent:
8327076, Dec 4, 2012
Filed:
May 13, 2009
Appl. No.:
12/465412
Inventors:
Robert D. Murphy - Boulder CO, US
Robert W. Dixon - Longmont CO, US
Steven S. Williams - Longmont CO, US
Robert W. Dixon - Longmont CO, US
Steven S. Williams - Longmont CO, US
Assignee:
Seagate Technology LLC - Cupertino CA
International Classification:
G06F 12/12, G06F 12/08
US Classification:
711136, 711135, 711E12071, 711E12022
Abstract:
The disclosure is related to data storage systems having multiple cache and to management of cache activity in data storage systems having multiple cache. In a particular embodiment, a data storage device includes a volatile memory having a first read cache and a first write cache, a non-volatile memory having a second read cache and a second write cache and a controller coupled to the volatile memory and the non-volatile memory. The memory can be configured to selectively transfer read data from the first read cache to the second read cache based on a least recently used indicator of the read data and selectively transfer write data from the first write cache to the second write cache based on a least recently written indicator of the write data.
System For Selectively Controlling Spin-Up Control For Data Storage Devices In An Array Using Predetermined Out Of Band (Oob) Signals
US Patent:
6915363, Jul 5, 2005
Filed:
Jun 10, 2002
Appl. No.:
10/167843
Inventors:
Robert Barry Wood - Niwot CO, US
Anthony Leigh Priborsky - Lyons CO, US
Robert William Dixon - Longmont CO, US
Anthony Leigh Priborsky - Lyons CO, US
Robert William Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G08F013/00, G08F015/167, G08F012/16, G08F012/14, G08F013/28
US Classification:
710 74, 710 5, 710 9, 710 10, 710100, 710300, 710305, 711114, 711 4
Abstract:
A data storage device array includes a number of data storage devices. Each of the disc drives is operable to spin-up its spindle motor in response to the successful communication of predetermined out-of-band (OOB) signals. By selectively causing the communication of the predetermined OOB signals to the data storage devices, the selective spin-up of the data storage devices may be achieved.
Dynamic Buffer Size Allocation For Multiplexed Streaming
US Patent:
7581043, Aug 25, 2009
Filed:
Nov 30, 2005
Appl. No.:
11/290061
Inventors:
Robert W. Dixon - Longmont CO, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G06F 3/00
US Classification:
710 52, 710 53, 710 54, 710 55, 710 56, 710 57
Abstract:
A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.