Robert D Brooks
Nursing at Plum, Fort Collins, CO
License number
Colorado 332429
Issued Date
Dec 16, 1995
Renew Date
Jan 31, 1998
Expiration Date
Jan 31, 1998
Type
Certified Nurse Aide
Address
Address
2155 W Plum St #5, Fort Collins, CO 80521
Professional information
Method Of Reading A Four-Transistor Memory Cell Array
US Patent:
6552925, Apr 22, 2003
Filed:
Jan 31, 2002
Appl. No.:
10/062079
Inventors:
Robert J Brooks - Fort Collins CO
Assignee:
Hewlett Packard Development Company, L.P. - Houston TX
International Classification:
G11C 1100
US Classification:
365154, 365156, 365207
Abstract:
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically ORing or ANDing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Method Of Querying A Four-Transistor Memory Array As A Content Addressable Memory By Rows Or Columns
US Patent:
6584002, Jun 24, 2003
Filed:
Jan 31, 2002
Appl. No.:
10/062053
Inventors:
Robert J Brooks - Fort Collins CO
Alexander J Neudeck - Windsor CO
Alexander J Neudeck - Windsor CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 1504
US Classification:
365 49, 365156, 365159, 365190, 36518907, 365226
Abstract:
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically ORing or ANDing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Method Of Reading And Logically Oring Or Anding A Four-Transistor Memory Cell Array By Rows Or Columns
US Patent:
6552924, Apr 22, 2003
Filed:
Jan 31, 2002
Appl. No.:
10/061876
Inventors:
Robert J Brooks - Fort Collins CO
Alexander J Neudeck - Windsor CO
Alexander J Neudeck - Windsor CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G11C 1100
US Classification:
365154, 365156, 365207
Abstract:
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically ORing or ANDing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Method Of Writing A Four-Transistor Memory Cell Array
US Patent:
6621728, Sep 16, 2003
Filed:
Jan 31, 2002
Appl. No.:
10/061925
Inventors:
Robert J Brooks - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
G11C 1100
US Classification:
365154, 365156
Abstract:
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically ORing or ANDing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Transparent Software Emulation As An Alternative To Hardware Bus Lock
US Patent:
6587964, Jul 1, 2003
Filed:
Feb 18, 2000
Appl. No.:
09/504023
Inventors:
Robert J Brooks - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714 28, 714 38, 710108
Abstract:
A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.
Method Of Optimization Of Cpu And Chipset Performance By Support Of Optional Reads By Cpu And Chipset
US Patent:
7051195, May 23, 2006
Filed:
Oct 26, 2001
Appl. No.:
10/002971
Inventors:
Blaine D. Gaither - Fort Collins CO, US
Robert J Brooks - Fort Collins CO, US
Robert J Brooks - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 13/18
US Classification:
712235, 712300
Abstract:
In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e. g. , bus controllers and switches, may similarly process speculative requests to enhance system performance.
Storage Element Reading Using Ring Oscillator
US Patent:
2013017, Jul 11, 2013
Filed:
Nov 1, 2010
Appl. No.:
13/823826
Inventors:
Robert J. Brooks - Fort Collins CO, US
International Classification:
G11C 13/00, G11C 7/00
US Classification:
365148, 365189011
Abstract:
Methods and apparatus are provided for use with data storage elements. A ring oscillator is coupled to a selected element within an array such that a feedback loop is defined. A period at oscillation for the ring oscillator is compared to a reference value. A data value stored within the selected element is determined accordingly. Stored data values remain essentially unaltered when accessed and read by way of the ring oscillator. Memory arrays having memristor or other storage elements can be used according to the present teachings.
Transparent Software Emulation As An Alternative To Hardware Bus Lock
US Patent:
2005006, Mar 17, 2005
Filed:
Oct 29, 2004
Appl. No.:
10/975400
Inventors:
Robert Brooks - Fort Collins CO, US
International Classification:
G06F011/00
US Classification:
714028000
Abstract:
One of the disclosed embodiments comprises a method for software emulation of hardware bus lock in a computer system, comprising: acquiring a bus lock semaphore; providing the bus lock semaphore to a device attempting a bus lock operation; acquiring a page table semaphore; invalidating page table entries to prevent access to a location in the computer system referenced by the bus lock operation, wherein the location is an input/output (I/O) device; purging translation lookaside buffer pages associated with the location; and executing a clone instruction without lock semantics.
Systems And Methods Of Synchronizing Reference Frequencies
US Patent:
7721133, May 18, 2010
Filed:
Apr 27, 2006
Appl. No.:
11/412384
Inventors:
Robert J Brooks - Fort Collins CO, US
Robert J. Blakely - Fort Collins CO, US
Karl J. Bois - Fort Collins CO, US
Robert J. Blakely - Fort Collins CO, US
Karl J. Bois - Fort Collins CO, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1/12, H03L 7/00
US Classification:
713400, 713500, 713503, 713600, 331 16, 331 17, 331 25, 331 34, 327 3
Abstract:
System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.
Robert Brooks
Location:
Fort Collins, Colorado Area
Industry:
Computer Hardware