Robert Cannon Bennion
Psychologist in Provo, UT

License number
Utah 100149-2501
Issued Date
Jan 1, 1911
Expiration Date
Dec 31, 1987
Category
Psychologist
Type
Psychologist
Address
Address
Provo, UT

Personal information

See more information about Robert Cannon Bennion at radaris.com
Name
Address
Phone
Robert Bennion
11773 S Currant Dr UNIT 111, South Jordan, UT 84095
Robert Bennion
447 S 500 E, Provo, UT 84606
(801) 295-6071
Robert Bennion, age 38
7266 S 2530 W, West Jordan, UT 84084
(801) 561-1720
Robert Bennion, age 44
711 S 1300 E, Salt Lake City, UT 84102
Robert Bennion, age 76
5882 S 150 W, Murray, UT 84107
(801) 266-5657

Professional information

See more information about Robert Cannon Bennion at trustoria.com
Robert Bennion Photo 1
Massively Parallel Vector Processing Computer

Massively Parallel Vector Processing Computer

US Patent:
4891751, Jan 2, 1990
Filed:
Mar 27, 1987
Appl. No.:
7/031697
Inventors:
Duane B. Call - Provo UT
Alfred Mudrow - Orem UT
Randall C. Johnson - Orem UT
Robert F. Bennion - Provo UT
Assignee:
Floating Point Systems, Inc. - Beaverton OR
International Classification:
G06F 1516, G06F 1300
US Classification:
364200
Abstract:
A massively parallel vector computer comprises a set of vector processing nodes, each node including a main processor for controlling access to a random access memory through an internal bus and a set of ports for interfacing external busses to the internal bus. The external busses interconnect pairs of nodes to form a network through which data may be transmitted from the random access memory in any one node to the random access memory in any other node in the network. Each vector processing node also includes a vector memory accessed through a local bus, the local and internal busses communicating via an additional port controlled by the main processor. A vector processor within each node performs operations on vectors stored in the vector memory and stores the results in the vector memory. A peripheral processing network comprises a set of peripheral processing nodes interconnected via further busses, and wherein selected peripheral processing nodes are coupled to selected vector processing nodes. The peripheral processing nodes are adapted to transmit data to and receive data from peripheral devices.