ROBERT BRICE BLANKENSHIP, M.D.
Osteopathic Medicine in Tacoma, WA
License number
Washington 35-076045
Category
Osteopathic Medicine
Type
Emergency Medicine
Address
Address
2
Madigan Army Medical Ctr, Tacoma, WA 98431
17818 92Nd Ave E, Puyallup, WA 98375
17818 92Nd Ave E, Puyallup, WA 98375
Phone
(253) 968-1250
Professional information
Robert Brice Blankenship, Tacoma WA
Specialties:
Emergency Medicine Physician
Address:
Madigan Army Medical Ctr, Tacoma, WA 98431
Board certifications:
American Board of Emergency Medicine Certification in Emergency Medicine
Pci Express Enhancements And Extensions
US Patent:
8230119, Jul 24, 2012
Filed:
Aug 23, 2010
Appl. No.:
12/861439
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Beaverton OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Bangalore, IN
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Abraham Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modlin, ID
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Beaverton OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Bangalore, IN
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Abraham Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modlin, ID
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00, G06F 13/20
US Classification:
710 5, 710313
Abstract:
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Pci Express Enhancements And Extensions
US Patent:
7899943, Mar 1, 2011
Filed:
Oct 31, 2007
Appl. No.:
11/933126
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar-Saba, IL
Avi (Arraham) Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modlin, IL
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar-Saba, IL
Avi (Arraham) Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modlin, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00, G06F 13/14
US Classification:
710 5, 710 6, 710305
Abstract:
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Pci Express Enhancements And Extensions
US Patent:
8230120, Jul 24, 2012
Filed:
Mar 28, 2011
Appl. No.:
13/073149
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar-Saba, IL
Abraham Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxbridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Kfar-Saba, IL
Abraham Mendelson - Haifa, IL
Ilan Pardo - Ramat-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00, G06F 13/14
US Classification:
710 5, 710 6, 710305
Abstract:
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Pci Express Enhancements And Extensions
US Patent:
2013013, May 23, 2013
Filed:
Dec 13, 2012
Appl. No.:
13/713635
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Saratoga CA, US
David J. Harriman - Portland OR, US
Mark B. Rosenbluth - Uxbridge MA, US
Ajay V. Bhatt - Portland OR, US
Peter Barry - Ardncrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert G. Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Avi Mendelson - Haifa, IL
Ilan Pardo - Ramat Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Saratoga CA, US
David J. Harriman - Portland OR, US
Mark B. Rosenbluth - Uxbridge MA, US
Ajay V. Bhatt - Portland OR, US
Peter Barry - Ardncrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert G. Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Avi Mendelson - Haifa, IL
Ilan Pardo - Ramat Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
International Classification:
G06F 13/42
US Classification:
710105
Abstract:
A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Method And Apparatus For The Synchronization Of Distributed Caches
US Patent:
8046539, Oct 25, 2011
Filed:
Jun 5, 2009
Appl. No.:
12/479541
Inventors:
Robert T. George - Austin TX, US
Mathew A. Lambert - Olympia WA, US
Tony S. Rand - Tacoma WA, US
Robert G. Blankenship - Tacoma WA, US
Kenneth C. Creta - Gig Harbor WA, US
Mathew A. Lambert - Olympia WA, US
Tony S. Rand - Tacoma WA, US
Robert G. Blankenship - Tacoma WA, US
Kenneth C. Creta - Gig Harbor WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/08
US Classification:
711141, 711146, 711144, 711E12026
Abstract:
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.
Multi-Node Chipset Lock Flow With Peer-To-Peer Non-Posted I/O Requests
US Patent:
7996572, Aug 9, 2011
Filed:
Jun 2, 2004
Appl. No.:
10/859891
Inventors:
Robert G. Blankenship - Tacoma WA, US
Robert J. Greiner - Beaverton WA, US
Herbert H. J. Hum - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US
Robert J. Greiner - Beaverton WA, US
Herbert H. J. Hum - Portland OR, US
Kenneth C. Creta - Gig Harbor WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00, G06F 7/38
US Classification:
710 5, 712 22
Abstract:
Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.
Pci Express Enhancements And Extensions
US Patent:
2013013, May 23, 2013
Filed:
Nov 30, 2012
Appl. No.:
13/690931
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Saratoga CA, US
David J. Harriman - Portland OR, US
Mark B. Rosenbluth - Uxbridge MA, US
Ajay V. Bhatt - Portland OR, US
Peter Barry - Ardncrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert G. Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Avi Mendelson - Haifa, IL
Ilan Pardo - Ramat Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Saratoga CA, US
David J. Harriman - Portland OR, US
Mark B. Rosenbluth - Uxbridge MA, US
Ajay V. Bhatt - Portland OR, US
Peter Barry - Ardncrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James Akiyama - Beaverton OR, US
Robert G. Blankenship - Tacoma WA, US
Ohad Falik - Kfar Saba, IL
Avi Mendelson - Haifa, IL
Ilan Pardo - Ramat Hasharon, IL
Eran Tamari - Ramat Gan, IL
Eliezer Weissmann - Haifa, IL
Doron Shamia - Modiin, IL
International Classification:
G06F 13/42
US Classification:
710314
Abstract:
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Pci Express Enhancements And Extensions
US Patent:
2008019, Aug 14, 2008
Filed:
Oct 31, 2007
Appl. No.:
11/933143
Inventors:
Jasmin Ajanovic - Portland OR, US
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxtridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
James Akiyama - Beavenon OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Klar-Saba, IL
Avi (Arraham) Mendelson - Halfa, IL
Ilan Pardo - Ramon-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Ellezer Weissmann - Halfa, IL
Doron Shamia - Modlin, IL
Mahesh Wagh - Portland OR, US
Prashant Sethi - Folsom CA, US
Debendra Das Sharma - Santa Clara CA, US
David Harriman - Portland OR, US
Mark Rosenbluth - Uxtridge MA, US
Ajay Bhatt - Portland OR, US
Peter Barry - Ardnacrusha, IE
Scott Dion Rodgers - Hillsboro OR, US
Anil Vasudevan - Portland OR, US
James Akiyama - Beavenon OR, US
Robert Blankenship - Tacoma WA, US
Ohad Falik - Klar-Saba, IL
Avi (Arraham) Mendelson - Halfa, IL
Ilan Pardo - Ramon-Hasharon, IL
Eran Tamari - Ramat Gan, IL
Ellezer Weissmann - Halfa, IL
Doron Shamia - Modlin, IL
International Classification:
G06F 9/46
US Classification:
718103
Abstract:
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Method And Apparatus For The Synchronization Of Distributed Caches
US Patent:
7546422, Jun 9, 2009
Filed:
Aug 28, 2002
Appl. No.:
10/231414
Inventors:
Robert T George - Austin TX, US
Mathew A Lambert - Olympia WA, US
Tony S Rand - Tacoma WA, US
Robert G Blankenship - Tacoma WA, US
Kenneth C Creta - Gig Harbor WA, US
Mathew A Lambert - Olympia WA, US
Tony S Rand - Tacoma WA, US
Robert G Blankenship - Tacoma WA, US
Kenneth C Creta - Gig Harbor WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/08
US Classification:
711145, 711146, 711141, 711129
Abstract:
A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.