Inventors:
Blaine D. Gaither - Fort Collins CO, US
Robert B. Smith - Lindon UT, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F012/00, G06F009/455
US Classification:
703 20, 703 21, 703 22, 711118, 711137, 711158, 711204, 714 47
Abstract:
A system and method for analyzing the effectiveness of a computer cache memory. A bus with memory transactions is monitored. A subset of addresses, along with associated transaction data, on the bus is captured and stored in a memory. The captured addresses are applied to a software model of a computer cache. The capture process is repeated multiple times, each time with a different subset of the address space. Statistical estimates of hit rate and other parameters of interest are computed based on the software model. Multiple cache configurations may be modeled for comparison of performance. Alternatively, a subset of addresses along with associated transaction data is sent to a hardware model of a cache. The contents of the hardware model are periodically dumped to memory or statistical data may be computed and placed in the memory. Statistical estimates of hit rate and other parameters of interest are computed based on the contents of the memory.