Robert Blaine Ash
Burglar Alarm in Austin, TX
License number
Utah 6730041-8009
Issued Date
Aug 29, 2007
Expiration Date
Nov 29, 2007
Category
Burglar Alarm
Type
Temporary Burglar Alarm Company Agent
Address
Address
Austin, TX
Professional information
Engineering Manager, Tennis Player
Position:
40nm Node Manager, Design Technologies at Freescale Semiconductor
Location:
Austin, Texas
Industry:
Semiconductors
Work:
Freescale Semiconductor
since Jun 2011
-
40nm Node Manager, Design Technologies
Freescale/Motorola Semiconductor
2001 - Jun 2008
-
Project Manager
Motorola Semiconductor
1998 - 2000
-
Product Manager
Motorola Semiconductor
1997 - 1998
-
Technology Introduction Manager
Motorola Semiconductor
1989 - 1998
-
Failure Analysis Lab Manager
Motorola Semiconductor
Jun 1984 - 1989
-
Failure Analysis Engineer
Education:
Georgia Institute of Technology (Georgia Tech) 1978 - 1984
Bachelor of Science, Physics Georgia Institute of Technology (Georgia Tech) 1978 - 1984
Bachelor of Engineering, Electrical Engineering
Bachelor of Science, Physics Georgia Institute of Technology (Georgia Tech) 1978 - 1984
Bachelor of Engineering, Electrical Engineering
Method And Apparatus For Performing Operative Testing On An Integrated Circuit
US Patent:
5929650, Jul 27, 1999
Filed:
Feb 4, 1997
Appl. No.:
8/795030
Inventors:
Bernard J. Pappert - Austin TX
Clark Shepard - Austin TX
Alfred Larry Crouch - Austin TX
Robert Ash - Austin TX
Clark Shepard - Austin TX
Alfred Larry Crouch - Austin TX
Robert Ash - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G01R 3128
US Classification:
324763
Abstract:
A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.