ROBERT AUGUST WHITE, M.D.
Osteopathic Medicine at Wilmot Rd, Tucson, AZ

4647906, Mar 3, 1987

Jun 28, 1985

6/750338

Jimmy R. Naylor - Tucson AZ
David F. Mietus - Tucson AZ
Robert L. White - Tucson AZ

Burr-Brown Corporation - Tucson AZ

H03K 1305

340347DA

An integrated circuit digital-to-analog converter includes a nichrome feedback resistor having. +-. 1% accuracy in its output amplifier, a plurality of bit current determining resistors that have. +-. 30% manufacturing accuracy, a bias voltage circuit that produces a temperature-compensated bias voltage including an integrated potentiometer that is laser trimmed to compensate for the inaccuracy of the bit current determining resistors. The bit current determining resistors thereby produce constant, precise temperature-independent bit currents. The integrated potentiometer is accurately laser trimmed without changing the series resistance of the potentiometer. This prevents current density changes that change the temperature sensitivity of temperature-compensating elements in the bias voltage circuit.

4800365, Jan 24, 1989

Jun 15, 1987

7/062774

Robert L. White - Tucson AZ
Frederick J. Highton - Tucson AZ
Kazuo Ito - Tucson AZ
Gary L. Miller - Santa Clara CA

Burr-Brown Corporation - Tucson AZ

H03M 106

341119

A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between V. sub. CC and a reference voltage that is adjusted to cause the on resistances of a P-channel "monitor" MOSFET and an N-channel "monitor" MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a V. sub. BE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the V. sub. BE voltage of a transistor and having a predetermined negative temperature coefficient, the second and third resistors being composed of nichrome, the first resistor being lightly doped P-type material the resistance of which has a positive temperature coefficient.

4593270, Jun 3, 1986

Jun 19, 1984

6/622259

Robert White - Tucson AZ

Burr-Brown Corporation - Tucson AZ

H03N 138

340347AD

An analog-to-digital converter is used in conjunction with a digital to analog converter and a comparison network to provide a group of digital signals that, when applied to a digital-to-analog converter, produce an output signal approximating an applied input signal. The analog-to-digital converter includes a clock circuit, a series of bistable multivibrator circuits, a master latch circuit, a plurality of slave latch circuits, and associated logic circuits. The bistable multivibrators are arranged to produce a sequence of activation signals in response to operation of the clock circuit. The activation signals serve to place slave latches circuits sequentially in a positive logic status temporarily, each slave latch output terminal being associated with a binary signal of decreasing significance in approximating the applied input signal. The output signal of the digital-to-analog converter is compared with the applied input signal. A signal resulting from the comparison of these signals is applied through the master latch circuit to the activated slave latch circuit and this comparison signal determines whether a positive or negative logic signal is latched at the output terminal of the slave latch circuit.

4381497, Apr 26, 1983

Apr 3, 1981

6/250858

William J. Lillis - Tucson AZ
Jimmy R. Naylor - Tucson AZ
Anthony D. Wang - Tucson AZ
Robert L. White - Tucson AZ

Burr-Brown Research Corporation - Tucson AZ

H03K 1305

340347DA

An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources. The open-loop voltage reference circuit is further adapted to compensate for second order errors caused by temperature induced variations in current gain and Early effect variations related to changes in the power supply voltage. A Gain Adjust feature is also provided for adjusting the bit switch currents without adversely affecting the regulation thereof.

7463075, Dec 9, 2008

Jun 23, 2006

11/473637

Robert L. White - Tucson AZ, US

Texas Instruments Incorporated - Dallas TX

H03K 3/017

327175, 327172

A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.

7642830, Jan 5, 2010

Oct 30, 2008

12/261941

Robert L White - Tuscon AZ, US

Texas Instruments Incorporated - Dallas TX

H03K 3/017

327175, 327172

A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.