ROBERT ARTHUR PATTERSON
Pilots at Jackson Quarry Rd, Beaverton, OR
License number
Oregon A1458805
Issued Date
Dec 2015
Expiration Date
Dec 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
13624 NW Jackson Quarry Rd, Beaverton, OR 97124
Personal information
See more information about ROBERT ARTHUR PATTERSON at radaris.comName
Address
Phone
51044 Greenway Dr, Gates, OR 97346
15521 Rose Pkwy, Portland, OR 97230
1756 Burns St, Klamath Falls, OR 97603
2150 Vine Ave, Klamath Falls, OR 97601
2177 Ohio St, Eugene, OR 97402
Professional information
Method Of Planarizing A Dielectric Formed Over A Semiconductor Substrate
US Patent:
5104828, Apr 14, 1992
Filed:
Mar 1, 1990
Appl. No.:
7/487418
Inventors:
Seiichi Morimoto - Beaverton OR
Robert J. Patterson - Beaverton OR
Robert J. Patterson - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21302, H01L 21463
US Classification:
437225
Abstract:
An improved method for planarizing the surface of an dielectric deposited over a semiconductor substrate. The substrate is pressed face down against a table which has been coated with an abrasive material. In this way, the upper surface of the interlayer dielectric contacts the abrasive. Rotational movement of the wafer relative to the table facilitates removal of the protruding portions of the interlayer dielectric by the abrasive. Post-planarization step height variation is minimized by simultaneously cooling the table and the abrasive material during the abrasive or polishing process. By maintaining the table and the abrasive at about 10 degrees Celsius the step height variation is reduced by a factor of 2 over that normally realized in the prior art.
Apparatus For Planarizing A Dielectric Formed Over A Semiconductor Substrate
US Patent:
5127196, Jul 7, 1992
Filed:
Feb 20, 1991
Appl. No.:
7/658019
Inventors:
Seiichi Morimoto - Beaverton OR
Robert J. Patterson - Beaverton OR
Robert J. Patterson - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B24B 2902
US Classification:
5116573
Abstract:
An improved method for planarizing the surface of an dielectric deposited over a semiconductor substrate. The substrate is pressed face down against a table which has been coated with an abrasive material. In this way, the upper surface of the interlayer dielectric contacts the abrasive. Rotational movement of the wafer relative to the table facilitates removal of the protruding portions of the interlayer dielectric by the abrasive. Post-planarization step height variation is minimized by simultaneously cooling the table and the abrasive material during the abrasive or polishing process. By maintaining the table and the abrasive at about 10 degrees Celcius the step height variation is reduced by a factor of 2 over that normally realized in the prior art.
Process For Filling Submicron Spaces With Dielectric
US Patent:
5270264, Dec 14, 1993
Filed:
Jul 21, 1992
Appl. No.:
7/917465
Inventors:
Ebrahim Andideh - Portland OR
Robert J. Patterson - Beaverton OR
Robert J. Patterson - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21465
US Classification:
437228
Abstract:
A process for filling submicron, high aspect ratio gaps, that may have reentrant angles, with a high quality ILD. A first ILD layer is deposited using PECVD to partially fill the gap. Medium-pressure sputter etching is then used to remove the bread-loaf edges and redeposit the etched material in the gaps, thereby allowing small gaps with high aspect ratios and reentrant angles to be completely filled. Finally, a second ILD layer that completely fills the gap is deposited using PECVD.