ROBERT ALAN MANSFIELD
Pilots at Ginita Ln, Austin, TX

4916301, Apr 10, 1990

Jan 17, 1989

7/298792

Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX

International Business Machines Corporation - Armonk NY

G09G 100

340747

A processing system is provided that includes an external device connected to a processor. The external device has the capability of responding to external device commands wherein each of these external device commands is performed within at least one fixed time cycle. The processor provides these external device commands and, further, includes the means for executing instructions that not only specify the external device commands but also specify at least one internal command to be performed by the processor simultaneously with the performance of the external device command and within the same fixed time cycle. In the disclosed embodiment, a graphics display system is provided that includes a system processor, a graphic processor, a graphics memory and a display device. The graphics processor receives instructions from the system processor which specifies commands to be executed by both the graphics processor and the graphics memory. Each graphics memory command is executed within a fixed time cycle simultaneously with the execution of a corresponding graphics processor command executed within the graphics processor.

4837563, Jun 6, 1989

Feb 12, 1987

7/013841

Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX

International Business Machine Corporation - Armonk NY

G09G 100

340732

In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter is performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a first predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reacing to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.

4808986, Feb 28, 1989

Feb 12, 1987

7/013840

Robert L. Mansfield - Austin TX
Marc Segre - Rhinebeck NY
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX

International Business Machines Corporation - Armonk NY

G09G 114

340747

A graphics display system including a circuit that receives graphics information to be displayed and a memory that stores the graphics information in a memory array that includes a portion that directly corresponds to the image area for display. The memory provides a single access operation to the array during a single memory cycle. Circuitry is provided that is connected to the receiving means and to the memory that provides graphics information to an N by M portion of the memory array during a single memory cycle (wherein N and M are integers each greater than one). A display is connected to the memory that displays the graphics information contained in the image area array portion of the memory. The graphics display system further includes the capability to provide a patterned line intersection where the continuity of the line pattern is maintained along the intersection of the lines.

4870406, Sep 26, 1989

Feb 12, 1987

7/013842

Satish Gupta - Peekskill NY
Leon Lumelsky - Stamford CT
Robert L. Mansfield - Austin TX
Hector G. Romero - Austin TX
Marc Segre - Rhinebeck NY
Alexander K. Spencer - Austin TX
Joe C. St. Clair - Round Rock TX
James D. Wagoner - Georgetown TX

International Business Machines Corporation - Armonk NY

G09G 128

340 70

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

4823286, Apr 18, 1989

Feb 12, 1987

7/013847

Leon Lumelsky - Stamford CT
Joe C. St. Clair - Round Rock TX
Robert L. Mansfield - Austin TX
Marc Segre - Rhinebeck NY
Alexander K. Spencer - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1206

364521

A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality "antialiased" text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the "burst" mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

5179709, Jan 12, 1993

Nov 14, 1990

7/611380

Roger N. Bailey - Austin TX
Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1300

395725

A technique for use in an I/O channel to increase bus bandwidth during DMA data transfers between main system memory and a communication link is disclosed, including a pair of buffers, a plurality of counters adapted to selectively contain a count of data increments therein, and enhanced DMA control logic for monitoring buffer data content amount, and at a predetermined time during a given transfer initiating a bus arbitration so that it is completed simultaneously with the given transfer, thereby enabling the next data transfer from the buffer in use to immediately commence.

5012435, Apr 30, 1991

Nov 17, 1988

7/273295

Roger N. Bailey - Austin TX
Robert L. Mansfield - Austin TX
Alexander K. Spencer - Austin TX

International Business Machines Corporation - Armonk NY

G06F 918, G04B 2312

364569

A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

5146572, Sep 8, 1992

Oct 4, 1990

7/593606

Roger N. Bailey - Austin TX
Robert L. Mansfield - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1200;13/00;3/00, G11C 800

395425

An interface circuit for providing an interface with the parallel data bus that transfers information in a multiple of formats. The interface includes a control circuit that receives or sends control signals from or to the parallel bus to regulate the data transfer and to specify one of the plurality of formats. An addressing circuit, connected to the control circuit, is provided for computing addresses for each of the data received or sent according to the specified format. An accessing circuit connected to the bus, control and address circuits is provided to store or retrieve data from or to the bus according to the computed data addresses. This interface provides a means to serialize data when, in one format, the first word of a data transfer is provided on one part of the data bus but, in a second format, the first data word is provided on another part of the data bus.