ROBERT ALAN DURIS
Pilots at Lombard Rd, Hubbardston, MA

License number
Massachusetts A0516357
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
36 Lombard Rd, Hubbardston, MA 01452

Personal information

See more information about ROBERT ALAN DURIS at radaris.com
Name
Address
Phone
Robert Duris, age 71
36 Lombard Rd, Hubbardston, MA 01452
(978) 928-5587
Robert S Duris
34 Canal St, Chicopee, MA 01013
(413) 557-6953
Robert S Duris
34 Canal St, Chicopee, MA 01013
(413) 557-6953
Robert S Duris, age 71
36 Lombard Rd, Hubbardston, MA 01452
(978) 928-5587
Robert W Duris, age 80
315 Beacon St, Lowell, MA 01850
(978) 453-1160

Professional information

See more information about ROBERT ALAN DURIS at trustoria.com
Robert Duris Photo 1
Driver Circuit With Low Power Termination Mode

Driver Circuit With Low Power Termination Mode

US Patent:
7199604, Apr 3, 2007
Filed:
Mar 26, 2004
Appl. No.:
10/811189
Inventors:
Bruce A. Hecht - Brookline MA, US
Robert Duris - Hubbardston MA, US
Warren Hambly - West Bridgewater MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 17/16, H03B 1/00
US Classification:
326 30, 327108, 327321
Abstract:
Driver circuits and methods for operating driver circuits in automatic test equipment are provided. The driver circuit includes an output circuit operable in a dynamic mode and in a termination mode, and a mode control circuit for supplying a first current to the output circuit in the dynamic mode and for supplying a second current to the output circuit in the termination mode in response to a mode select signal. The mode control circuit may include a current multiplier and a switching circuit for switching a control current supplied to the current multiplier. In one example, the slew current supplied to the output circuit is controlled in response to the mode select signal.


Robert Duris Photo 2
Automatic Test Equipment Pin Channel With T-Coil Compensation

Automatic Test Equipment Pin Channel With T-Coil Compensation

US Patent:
7248035, Jul 24, 2007
Filed:
Nov 25, 2003
Appl. No.:
10/722970
Inventors:
Douglas W. Babcock - Manchester NH, US
Robert A. Duris - Hubbardston MA, US
Bruce Hecht - Brookline MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G01R 27/26
US Classification:
3241581, 324 731
Abstract:
A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.


Robert Duris Photo 3
Programmable Clamp For Output Circuit

Programmable Clamp For Output Circuit

US Patent:
6507231, Jan 14, 2003
Filed:
Aug 24, 2001
Appl. No.:
09/939201
Inventors:
Bruce Hecht - Brookline MA
Stephan Goldstein - Reading MA
Robert Duris - Hubbardston MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H03K 508
US Classification:
327321
Abstract:
A clamp for use with a circuit (having an output for delivering an output voltage) forms a voltage boundary for the output voltage based upon a clamp voltage. To that end, the clamp includes a clamp input for receiving the clamp voltage, a clamp transistor in communication with the clamp input, and a control transistor in communication with the output. The clamp also includes a driving source for driving at least one of the clamp and control transistors based upon the voltage at the clamp input and the voltage at the output. The output is clamped at a voltage within the voltage boundary of the clamp voltage after the clamp transistor begins being driven by the driving source.


Robert Duris Photo 4
Circuit And Method Of Providing Thermal Compensation For A Transistor To Minimize Offset Voltage Due To Self-Heating Of Associated Devices

Circuit And Method Of Providing Thermal Compensation For A Transistor To Minimize Offset Voltage Due To Self-Heating Of Associated Devices

US Patent:
5424510, Jun 13, 1995
Filed:
Aug 27, 1993
Appl. No.:
8/113397
Inventors:
Alex Gusinov - Brighton MA
A. Paul Brokaw - Burlington MA
Douglas W. Babcock - Manchester NH
Lewis Counts - Lexington MA
Lawrence DeVito - Tewksbury MA
Robert A. Duris - Hubbardston MA
Scott Wurcer - Cambridge MA
Assignee:
Analog Devices Inc. - Norwood MA
International Classification:
H05B 302
US Classification:
219209
Abstract:
A circuit for varying the temperature of a first bipolar transistor in order to thermally compensate for self-heating effects of an associated device in a common signal path with the first transistor, the first transistor being configured within an isolated collector region. The circuit includes a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor, the second transistor operable for providing heat to the first transistor to alter the temperature to a predetermined level, thus changing the operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage.


Robert Duris Photo 5
Parasitic Capacitance Cancellation Circuit

Parasitic Capacitance Cancellation Circuit

US Patent:
5434446, Jul 18, 1995
Filed:
Aug 8, 1994
Appl. No.:
8/287478
Inventors:
Edward B. Hilton - Wayland MA
Robert A. Duris - Hubbardston MA
Douglas W. Babcock - Manchester NH
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 2712, H01L 2702
US Classification:
257503
Abstract:
A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.


Robert Duris Photo 6
T-Coil Apparatus And Method For Compensating Capacitance

T-Coil Apparatus And Method For Compensating Capacitance

US Patent:
7470968, Dec 30, 2008
Filed:
Jan 4, 2006
Appl. No.:
11/325882
Inventors:
Douglas W. Babcock - Manchester NH, US
Robert A. Duris - Hubbardston MA, US
Bruce Hecht - Brookline MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 27/08
US Classification:
257531, 257E21575, 257566, 257578, 257728, 3241581, 324763, 324765
Abstract:
A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.