ROBERT A RYAN
Real Estate Commission in Langhorne, PA

7093082, Aug 15, 2006

Jun 11, 2003

10/458999

Robert T. Ryan - Langhorne PA, US

Matsushita Electric Industrial Co., LTD - Osaka

G06F 12/00, G06F 9/26

711147, 718101, 718102, 711105, 711150, 711217, 711221

An SDRAM controller includes a service unit for receiving an SDRAM service request from at least one requester; a memory for storing instructions for performing a plurality of SDRAM transactions; and a lookup table of a sequence of addresses corresponding to at least a portion of the instructions stored in the memory, the portion of the instructions defining the SDRAM transaction. The service unit is configured to execute the SDRAM transaction based on the sequence of addresses in the lookup table. Also included is an arbiter for receiving service requests from multiple requestors to access the SDRAM, and another lookup table of identifiers corresponding to the multiple requestors, the identifiers stored in another sequence of addresses. The arbiter is configured to sequentially access each address in the other sequence of addresses, and grant service to a requestor based on an identifier stored in an address accessed.

5812976, Sep 22, 1998

Mar 29, 1996

8/623948

Robert T. Ryan - Langhorne PA

Matsushita Electric Corporation of America - Secaucus NJ

G10L 302, G10L 900, H04J 300

704201

A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122. To properly interface to a bitrate-constrained audio decoder, the PES headers of received data are stripped and parsed (step 530), a frame time is determined (step 532), the timer begins running (step 534), audio processors 226/228 burst out a frame of data (step 536) and audio processors 226/228 pause (step 538). After the burst, the audio processor determines (step 540) if more audio frames are available in the current packet. If more frames are available, control transfers to (step 534) and the process continues as outlined above. If there are no more frames in the PES packet, then, (step 542) is executed in which the audio processor gets the next PES packet from the memory 114 and transfers control to (step 530) to process the audio frames in the new PES packet.

5675654, Oct 7, 1997

Mar 29, 1996

8/626176

Robert T. Ryan - Langhorne PA

Matsushita Electric Corporation of America - Secaucus NJ

H04N 7167

380 48

A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122. The transport decoder also includes an interface to a decoder which does not include a "data valid" input terminal. Upon receipt of encoded data packets, the transport decoder recognizes a frame synchronization byte and transfers an encoded data packet to an external decoder via the interface. The transport decoder sets a count value for a predetermined number of bytes in the encoded data packet and sends the packet data to the external decoder. When the specified number of bytes have been sent to the external decoder, the transport decoder determines if another synchronization byte has been encountered. If another synchronization byte has been found, the transport decoder continues to send encoded data to the decoder.

6539120, Mar 25, 2003

Mar 15, 1999

09/180154

Richard Sita - Audubon NJ
Saiprasad Naimpally - Langhorne PA
Larry Phillips - Cherry Hill NJ
Edwin Robert Meyer - Bensalem PA
Robert T. Ryan - Langhorne PA
Ghanshyam Dave - Marlton NJ
Edward Brosz - King of Prussia PA
Jereld Pearson - Mt. Ephraim NJ

Matsushita Electric Industrial Co., Ltd. - Osaka

G06K 932

382233, 382238, 382239, 382250, 382251, 382246, 382260, 382298, 382299, 382300, 37524001, 37524002, 37524003, 37524025

A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which, when the decoder is operated in a first mode, decodes a Main Profile, High Level (MP HL) image to produce a high-definition video output signal and decodes a Main Profile, Main Level (MP ML) signal to produce a standard definition video signal. In addition, when the decoder is operated in a second mode, circuitry is used which generates a standard definition image from the MP HL signal. The video decoder includes a frequency-domain filter to reduce the resolution of the MP HL signal when the decoder is operated in the second mode.

6522694, Feb 18, 2003

Oct 9, 1998

09/169791

Robert T. Ryan - Langhorne PA

Matsushita Electric Industrial Co., Ltd. - Osaka

H04N 712

37524025

An MPEG-2 video decoder which identifies and removes stuffing data from an MPEG-2 bit-stream before storing the bit-stream into the VBV buffer of the decoder. The decoder monitors the MPEG-2 bit-stream for successive groups of zero-valued bytes. When a sequence of successive of zero-valued bytes is encountered that is greater than a programmed maximum length the decoder identifies the sequence as stuffing data and inhibits any further zero-valued bytes from being passed until the next non-zero valued byte is encountered. The decoder specifies two maximum length values, one for the number of stuffing bytes which may precede a Slice start code and the other for the number of stuffing bytes which may precede a non-Slice code. These values may be changed during the decoding operation by a microprocessor.

6366617, Apr 2, 2002

Oct 9, 1998

09/169331

Robert T. Ryan - Langhorne PA

Matsushita Electric Industrial Co., Ltd. - Osaka

H04N 712

37524025, 37524026, 37524029

An MPEG- video decoder which identifies and removes selected User Data fields from an MPEG- bit-stream before storing the bit-stream into the VBV buffer of the decoder. The decoder monitors the MPEG- bit-stream with a state machine to determine the level of the record (Sequence, Group of Pictures or Picture) that is currently being decoded. The decoder also monitors the bit-stream for User Data Start Codes. When a User Data Start Code is encountered, the state of the state machine is compared to preprogrammed commands provided by a microprocessor. Only if these commands require the decoding of User Data at a particular level will the User Data following the User Data Start Code be passed to the VBV buffer. The commands provided by the microprocessor may be changed to selectively inhibit the storage of more or less User Data depending on the identified need for the User Data and the relative burden that processing the User Data through the VBV buffer places on the decoder.

6263019, Jul 17, 2001

Oct 9, 1998

9/169580

Robert T. Ryan - Langhorne PA

Matsushita Electric Industrial Co., Ltd. - Osaka

H04B 166

37524002

An MPEG-2 video signal decoder includes a syntax parser which is implemented as a state machine. The state machine defines a plurality of states in which discrete parsing operations are performed to decode the MPEG-2 bit-stream. A distinct processing time is established for each state in the state machine. Even if the processing for a particular state is complete before the end of the respective processing time for the state, the transition from the state to the next state does not occur until the end of the time interval. The processing time for each state is set by a microprocessor coupled to the state machine. The processing time for each state may be changed based on image content or to accommodate changes in the circuitry used to implement the state machine. The processing times for the states may also be adjusted to accommodate changes in other processing elements, separate from the state machine but which depend on the state machine for the processing that they perform. One way in which the processing times may be changed is to conform the processing of an image or a sequence of images to a predetermined maximum time interval.

5818539, Oct 6, 1998

Mar 29, 1996

8/626184

Saiprasad V. Naimpally - Langhorne PA
Joseph P. O'Hara - Medford NJ
Edwin Robert Meyer - Bensalem PA
Robert T. Ryan - Langhorne PA

Matsushita Electric Corporation of America - Secaucus NJ

H04L 700

348512

A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122. Upon receipt of a discontinuity indicator, the transport packet headers are parsed and transport packet payloads are stored in memory. Subsequently, upon receipt of a next program counter reference (PCR) value, a counter is loaded with the received program counter reference value. Next, the data stored in memory is searched for a time stamp and, when one is found, the time stamp is retrieved. Finally, a timer interrupt is set for a point in time approximately one frame time before the time stamp value, and, when the timer interrupt occurs, the program counter reference value is sent to the decoders, thereby providing sufficient time for the decoders to process data.

5828416, Oct 27, 1998

Mar 29, 1996

8/623878

Robert T. Ryan - Langhorne PA

Matsushita Electric Corporation of America - Secaucus NJ

H04N 9475

348512

A transport decoder 110, for receiving and processing a transport data stream using MPEG-2 formats, includes connections to a physical layer channel interface (channel interface) 112, a buffer memory 114, a host microprocessor 116, audio and video decoders 118/120, and clock signal circuitry 122. To properly interface with a video decoder requiring an elementary datastream, the headers of received data are stripped and parsed (step 510), timestamp information is stored and a byte count is maintained (step 512), an interrupt is issued by video processor 224 to microprocessor 116 alerting it that timestamp information is available for reading (step 514), if additional timestamp information is received before microprocessor reads the previous timestamp information, the new timestamp information is stored, the byte count continues to accumulate (step 516) and the video processor 224 issues another interrupt to the microprocessor 116 (step 514), otherwise microprocessor reads the status register, the timestamp information and the byte count information and delivers it to the external video decoder (step 518).

4998214, Mar 5, 1991

Apr 3, 1989

7/331778

Robert T. Ryan - Langhorne PA

Unisys Corp. - Blue Bell PA

G01D 1500

364519

A high speed real time print head controller is provided for supporting a high resolution vector graphics command set which is employed to perform flexible high speed generation of textured line effects. Rows of continuous graphics line information are generated by a print head controller and modified by novel texture control means and style control means so that the bit information supplied to a shift alignment means under control of the style logic means is loaded into a bit map memory one parallel word at a time to completely load a page of information in the bit map memory in the desired styled and textured pixel format for presentation to a write head buffer for printout.