ROBERT A MARTIN
Electrician at China Tree Dr, Dallas, TX

License number
Texas 50042
Expiration Date
Jul 24, 2017
Category
Journeyman Electrician
Address
Address
10210 China Tree Dr, Dallas, TX 75249
Phone
(817) 578-1001

Organization information

See more information about ROBERT A MARTIN at bizstanding.com

ROBERT MARTIN, M.D., PA

7777 Frst Ln STE C430, Dallas, TX 75230

Industry:
Obgyn
Doing business as:
Robert Martin, M.D., PA
Registration:
Jul 16, 2003
State ID:
0800225456
Business type:
Professional Association
Member , Director, President:
Robert Martin (Member , Director, President)
TIN:
32035748469
Categories:
Gynecology & Obstetrics Physicians & Surgeons
In practice since:
1969
Customers served:
Commercial, Residential
Additional:
Small Jobs Welcome

Professional information

Robert Martin Photo 1

It Consultant

Position:
Sr. Consultant at Fluid Consulting
Location:
Dallas/Fort Worth Area
Industry:
Information Technology and Services
Work:
Fluid Consulting since Apr 2009 - Sr. Consultant Robert Martin Oct 2008 - Apr 2009 - Independent Contractor VLP Corporate Services, LLC Apr 2004 - Oct 2008 - Vice President Technology DCSS Apr 1998 - Mar 2004 - Sr. Consultant Digital Consulting & Software Services 1998 - 2004 - Consultant Campo E A & C 1993 - Apr 1998 - Store Manager
Education:
Loyola University New Orleans 1987 - 1992
BS, Physics
Interests:
Networking, new technologies, personal improvement


Robert Martin Photo 2

Tube Fitting Having A Saddle Bead With Conforming Pilot

US Patent:
5056704, Oct 15, 1991
Filed:
Feb 22, 1988
Appl. No.:
7/158797
Inventors:
Robert E. Martin - Dallas TX
Richard B. Martin - Carrollton TX
Assignee:
Tube Forming, Inc. - Carrollton TX
International Classification:
B23K 3102
US Classification:
2281734
Abstract:
A method and product for forming a joint between intersecting sections of tubing for the conduct of fluid flow. For forming the joints, there is included a section of primary tubing which is drilled or punched to form a radial aperture defining the location at which the joint is to be formed. To effect joinder with the primary tube, there is provided a secondary tube having an end that includes a pilot portion extending rearward from a recessed end plane and which merges with an integrally shaped saddle bead formed about the tube periphery. Inserting the pilot end of the secondary tube into the provided aperture of the primary tube enables the saddle bead to incur a contour overlay against the outside diameter of the primary tube for effecting lateral alignment therebetween while enabling joinder by welding, brazing or soldering. Also disclosed is the method of forming the secondary tube to produce a recessed end face/saddle bead combination by the use of upsetting swaging dies.


Robert Martin Photo 3

Translator Circuit And Method Of Operation

US Patent:
5027014, Jun 25, 1991
Filed:
Mar 30, 1990
Appl. No.:
7/502471
Inventors:
Alan S. Bass - Plano TX
Stephen R. Schenck - McKinney TX
Robert C. Martin - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 19092, H03K 19094, H03K 19086, H03K 19003
US Classification:
307475
Abstract:
There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from negative voltage levels to positive voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.


Robert Martin Photo 4

Teacher At School For The Talented And Gifted, Dallas Isd

Position:
Teacher at School for the Talented and Gifted, Dallas ISD
Location:
Dallas/Fort Worth Area
Industry:
Computer Software
Work:
School for the Talented and Gifted, Dallas ISD - Teacher


Robert Martin Photo 5

Robert Martin - Dallas, TX

Work:
Mid-Am Metal Forming Dreamworks Construction
Laborer
Carr Apartments - Terrell, TX
Maintenance Manager
Education:
Terrell High School - Terrell, TX
High School Diploma


Robert Martin Photo 6

Robert Martin

Location:
Dallas/Fort Worth Area
Industry:
Hospital & Health Care


Robert Martin Photo 7

A High Speed, Non-Inverting Circuit For Providing An Interface Between Ttl Logic Gates And Schottky Transistor Logic Gates

US Patent:
4536664, Aug 20, 1985
Filed:
Feb 16, 1983
Appl. No.:
6/467105
Inventors:
Robert C. Martin - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 19092, H03K 19084, H03K 19013
US Classification:
307475
Abstract:
A high speed, noninverting circuit for providing an interface between transistor-transistor logic gates and Schottky transistor logic gates. In one embodiment the output of a TTL circuit is coupled through a Schottky diode to an emitter-follower whose input is Schottky clamped. The output of the emitter-follower is coupled to a constant current sink and to the cathode of a low barrier Schottky diode, the anode of which forms the STL-compatible output of the interface circuit. The present circuit thus performs a noninverting level translation with minimum propagation delay.


Robert Martin Photo 8

Socket For Housing A Plurality Of Integrated Circuits

US Patent:
4364620, Dec 21, 1982
Filed:
Sep 5, 1980
Appl. No.:
6/261236
Inventors:
Wayne A. Mulholland - Plano TX
Robert J. Martin - Dallas TX
David S. Wilson - Fort Collins CO
Carlos Esparza - Lewisville TX
Assignee:
Mostek Corporation - Carrollton TX
International Classification:
H01R 1300
US Classification:
339 17CF
Abstract:
A socket (10) is described for housing similar integrated circuits (#1, #2). The socket (10) comprises a center support (14) which includes integral end panels (14a, 14b). The center support further includes a plurality of upstanding separators (42, 44) which form a plurality of recesses (46, 48). Side panels (18, 20) are joined to the center support to form first and second chambers (23, 24). A bottom plate (16) is connected to the center support (14) and side panels (18, 20). A lead frame (22) is positioned within the first and second chambers to provide metallic strips within the recesses (46, 48). In certain of the recesses the metallic strips extend from corresponding recesses in the two chambers (23, 24) and connect to a respective socket lead (12). In other selected recesses a metallic strip extends directly to connect to a package lead (12) such that there is no direct connection between common recesses. The integrated circuits (#1, #2) are positioned within the chambers (23, 24) such that the leads of the integrated circuits (#1, #2) are received within the recesses (46, 48).


Robert Martin Photo 9

High Speed Flip-Flop For Gate Array

US Patent:
5612632, Mar 18, 1997
Filed:
Nov 29, 1994
Appl. No.:
8/346562
Inventors:
Shivaling Mahant-Shetti - Los Angeles CA
Kevin Ovens - Plano TX
Clive Bittlestone - Allen TX
Robert C. Martin - Dallas TX
Robert J. Landers - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 19173, H03K 1900
US Classification:
326 46
Abstract:
A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal.


Robert Martin Photo 10

Fine Resolution Digital Delay Line With Coarse And Fine Adjustment Stages

US Patent:
5544203, Aug 6, 1996
Filed:
Oct 18, 1994
Appl. No.:
8/324856
Inventors:
Joseph A. Casasanta - Allen TX
Bernhard H. Andresen - Dallas TX
Yoshinori Satoh - Plano TX
Stanley C. Keeney - Dallas TX
Robert C. Martin - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03D 324
US Classification:
375376
Abstract:
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.