Robert A Kenney
Engineers at Shavano Dr, Austin, TX

7610537, Oct 27, 2009

Apr 4, 2006

11/278615

Dan Jeffrey Dickinson - Essex Junction VT, US
Robert D. Kenney - Austin TX, US
Christina Lynne Newman-LaBounty - Stowe VT, US
Ronald Gene Walther - Austin TX, US

International Business Machines Corporation - Armonk NY

G01R 31/28, G06F 11/00

714733, 714734, 714 30

A computer implemented method, data processing system, and computer usable code are provided for testing multi-core microprocessors. A test process initiates testing on communication bus interfaces associated with a set of processor cores on the multiprocessor in which the communication bus interfaces are disabled and wherein the testing uses a set of isolation test sequences to obtain results. The process identifies a set of functional processor cores in the set of processor cores based upon the results. The process also initiates a ramp logic built-in self-test to test a ramp associated with a functional processor core in the set of functional processor cores, wherein the ramp logic built-in self-test determines if the communication bus interface associated with functional processor core in the set of functional processor cores is functional.

8397190, Mar 12, 2013

Aug 2, 2011

13/196005

Robert D. Kenney - Austin TX, US
Raymond C. Yeung - Round Rock TX, US
Paul K. Miller - Dripping Springs TX, US
Donald W. Glowka - Austin TX, US
Jeffrey B. Reed - Austin TX, US

Apple Inc. - Cupertino CA

G06F 17/50

716106, 716110, 716124, 716126, 716131, 716132, 716136, 716138, 716139, 703 13, 703 14

A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.

2014007, Mar 13, 2014

Sep 13, 2012

13/613184

Michael R. Seningen - Austin TX, US
Gregory D. Roberts - Austin TX, US
Robert Kenney - Austin TX, US
James De Leon - Austin TX, US

H03K 19/173, H03K 19/00

326 16, 326 46, 326 38

A circuit for implementing latch array functions on an integrated circuit. Portions of the logic devices included in the implementation of the latch array functions that are controlled by a common signal, may be arranged in a particular alignment. A single layer uni-directionally conductive material may connect the common signal to the logic devices.

2013011, May 9, 2013

Nov 8, 2011

13/291703

William V. Miller - Austin TX, US
Robert D. Kenney - Austin TX, US
Charles E. Pope - Austin TX, US

G06F 3/00

710 52

Techniques are disclosed relating to buffer circuits. In one embodiment, a buffer circuit is disclosed that includes memory unit and an output register. The memory unit is configured to store a plurality of buffer entries and a first pointer to a current one of the plurality of buffer entries. The output register is coupled to an output of the memory unit. The buffer circuit is configured to perform a read operation by outputting a current value of the output register and storing a value of the current buffer entry in the output register. The buffer circuit is configured to update the first pointer in response to the read operation.

8484589, Jul 9, 2013

Oct 28, 2011

13/283665

Robert D. Kenney - Austin TX, US
Hani Hasan Mustafa Saleh - Austin TX, US
Sreevathsa Ramachandra - Austin TX, US

Apple Inc. - Cupertino CA

G06F 17/50

716105, 716100, 716103, 716104, 716106, 716108

During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.

2012014, Jun 7, 2012

Jun 10, 2011

13/157515

Robert D. Kenney - Austin TX, US

G06F 17/30

707745, 707E17057

An integrated circuit includes a search unit configured to access an input vector including a number of bits, and to find a first and a second instance of a predetermined bit value such as a logic zero or a logic one, for example. The search unit may be further configured to generate an output that includes an indication of a bit position of the first instance of the predetermined bit value within the input vector, and an indication of a bit position of the second instance of the predetermined bit value within the input vector.