RICHARD W SMITH
Massage Therapy at Camino Real, Boca Raton, FL

3972023, Jul 27, 1976

Dec 30, 1974

5/537471

Ronald E. Bodner - Rochester MN
Mario N. Cianciosi - Rochester MN
Thomas L. Crooks - Rochester MN
Israel B. Magrisso - Coral Springs FL
Keith K. Slack - Rochester MN
Richard S. Smith - Boca Raton FL

International Business Machines Corporation - Armonk NY

G06F 300

3401725

Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock.

3961313, Jun 1, 1976

Dec 4, 1974

5/529677

Ronald E. Bodner - Rochester MN
Thomas L. Crooks - Rochester MN
Israel B. Magrisso - Coral Springs FL
Keith M. Slack - Rochester MN
Richard S. Smith - Boca Raton FL

International Business Machines Corporation - Armonk NY

G06F 918

3401725

The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.