RICHARD SIMPSON, M.D.
Medical Practice in Houston, TX

4713748, Dec 15, 1987

Feb 12, 1985

6/701827

Surendar S. Magar - Houston TX
Daniel L. Essig - Houston TX
Richard D. Simpson - Houston TX
Edward R. Caudel - Stafford TX

Texas Instruments Incorporated - Dallas TX

G06F 1300

364200

A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16. times. 16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space. The processor may operate with all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from off-chip program memory) using a block move instruction.

5122738, Jun 16, 1992

Oct 9, 1990

7/594517

Richard D. Simpson - Houston TX
Iain C. Robertson - Bedford, GB2

Texas Instruments Incorporated - Dallas TX

G01R 3128

324158R

A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data into the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor. During testing the series connected transistor is blocked and the first latch element is connected in a two elements per bit shift register configuration with the second latch element by series connected transistors controlled by antiphase square waves.

5101127, Mar 31, 1992

Jan 25, 1991

7/649204

Richard Simpson - Houston TX

Texas Instruments Incorporated - Dallas TX

H03K 906, H03K 522

307518

A digital integrated circuit normally operated from an external clock signal and including an internal reference oscillator for providing a reference signal as an internally generated signal backup in the event that the external clock signal is not present or is too low in frequency for safe operation of the integrated circuit. The integrated circuit has a frequency comparator for receiving the external clock signal and the internal reference signal as inputs and producing an output indicative of the state of the external clock signal. A two-way switch is connected to the output of the frequency comparator and selects either the external clock signal or the internal reference signal for transmission to the integrated circuit based upon the output from the frequency comparator. The frequency comparator includes a frequency discriminator which has two parts for providing respective complementary output logic signals when the external clock signal is consistently at either the high logic level or the low logic level, and for respectively providing the same output logic signal when the external clock signal alternates between the high and low logic levels. An output circuit is connected to the outputs of the first and second parts of the frequency discriminator for combining the output signals of the first and second parts in producing the output of the frequency comparator as provided to the two-way switch.

4774471, Sep 27, 1988

Nov 13, 1986

6/929871

Jackie C. Sims - Houston TX
Percy T. Cox - Houston TX
Richard S. Simpson - Houston TX

Texaco Inc. - White Plains NY

G01V 310, G01V 318

324341

A well logging system and method for determining the water saturation of an earth formation and the resistivity of the water using complex dielectric constant and formation porosity measurements. Electromagnetic energy is transmitted into the earth formation from a borehole at a frequency lying within the range of frequencies from 10 MHz to 200 MHz. Electromagnetic energies are received at two locations in the borehole. A complex dielectric constant is derived from the received electromagnetic energies. The water resistivity and the water saturation of the earth formation is derived in accordance with the porosity of the earth formation and with the real and imaginary parts of the derived complex dielectric constant.

4558232, Dec 10, 1985

Feb 22, 1982

6/350958

Richard D. Simpson - Houston TX

H03K 5153, H03K 524

307351

An overvoltage detector circuit for connection to an input terminal of a microcomputer device or the like employs a bistable latch with two inputs, one connected to a reference potential and the other to the input terminal. When the inputs are gated, the latch flips to one state if the terminal is at an overvoltage, or the other state if the terminal is at zero or logic-1. This circuit may be used to institute a test mode for the microcomputer.

5005193, Apr 2, 1991

Jun 29, 1989

7/374194

Richard D. Simpson - Houston TX

Texas Instruments Incorporated - Dallas TX

H03K 519, H03K 2112

377 33

A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

4794380, Dec 27, 1988

Jul 21, 1987

7/078301

Jack A. Dennison - Waller TX
Richard S. Simpson - Houston TX

Texaco Inc. - White Plains NY

G08B 2100

340672

A magnet and two magnetic sensing means are spatially related to each other, with each magnetic sensor sensing the relative movement between the magnet and the magnetic sensor. The magnetic sensor provides a signal corresponding to the relative movement. Circuitry connected to both magnetic sensors provides an alarm in accordance with the signals from both magnetic sensors when the rotation of the crank arm is in one direction and does not provide an alarm when the rotation of the crank arm is in the opposite direction.

4992727, Feb 12, 1991

Jun 28, 1989

7/373123

Richard D. Simpson - Houston TX
Iain C. Robertson - Bedford, GB2

Texas Instruments Incorporated - Dallas TX

G01R 3128

324158R

A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data in the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor. During testing the series connected transistor is blocked and the first latch element is connected in a two elements per bit shift register configuration with the second latch element by series connected transistors controlled by antiphase square waves.