RICHARD R BELL
Pilots at Silver St, Mechanicsburg, VT
License number
Vermont A4999586
Issued Date
May 2015
Expiration Date
May 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
593 Silver St, Mechanicsburg, VT 05461
Professional information
Fast/Slow State Machine Latch
US Patent:
7459936, Dec 2, 2008
Filed:
Oct 10, 2007
Appl. No.:
11/869988
Inventors:
Richard R. Bell - Hinesburg VT, US
Wilson D. Skipwith - Essex Junction VT, US
Sebastian T. Ventrone - Burlington VT, US
Wilson D. Skipwith - Essex Junction VT, US
Sebastian T. Ventrone - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 7/38, H03K 19/173
US Classification:
326 46, 326 52, 327144
Abstract:
A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.
Fast/Slow State Machine Latch
US Patent:
7331021, Feb 12, 2008
Filed:
Oct 28, 2005
Appl. No.:
11/163750
Inventors:
Richard R. Bell - Hinesburg VT, US
Wilson D. Skipwith - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US
Wilson D. Skipwith - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US
Assignee:
International Business Machines, Inc. - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 2, 716 6
Abstract:
A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.