RICHARD LEE COULSON
Pilots at Gilbert Ln, Portland, OR

5802069, Sep 1, 1998

Mar 28, 1996

8/627939

Richard Coulson - Portland OR

Intel Corporation - Santa Clara CA

G06F 1100

371 211

A computer system comprises a host processor, host memory, and a mass storage device interconnected via a high-speed data bus. An operating system and a driver for the mass storage device are implemented on the host processor. The mass storage device is capable of being connected to the computer system via the data bus, such that a portion of the host memory is allocated for use by the mass storage device; the mass storage device uses the host memory portion for one or more particular mass storage device operations; and the operating system and the driver are unaware of how the mass storage device uses the host memory portion. In a preferred embodiment, the mass storage device requests and the host processor allocates a portion of host memory for exclusive use by the mass storage device to perform such functions as predictive failure analysis, maintenance of deallocated sector lists, and data prefetching.

6915376, Jul 5, 2005

Dec 22, 1998

09/218037

Richard L. Coulson - Portland OR, US
Knut S. Grimsrud - Forest Grove OR, US

Intel Corporation - Santa Clara CA

G06F012/00

711112

A method, apparatus and computer program for causing a host computer to optimize execution of plural requests for access to plural data storage locations on a rotating disk, included in a disk storage device, based on a rotational position of the disk relative to a position of a read/write head. The host computer stores position information representing a rotational position of the disk, detects whether plural requests are to be executed, and when plural requests are to be executed, optimizes execution of the requests by reordering a sequence of execution of the requests in a manner to reduce a total service time of the requests based on the position information.

6009527, Dec 28, 1999

Oct 23, 1997

8/959101

C. Brendan S. Traw - Hillsboro OR
Eric C. Hannah - Pebble Beach CA
Jerrold V. Hauck - Fremont CA
Richard L. Coulson - Portland OR
Brad W. Hosler - Portland OR

Intel Corporation - Santa Clara CA

G06F 1214

713200

Security from an unwanted intrusion into a computer system is provided by coupling a host component with a peripheral component using a high-speed serial bus having a high-speed physical layer and using features of the bus to implement the security. In an embodiment, the high-speed serial bus has a secondary bus layer that is used to implement a number of the security features of the invention.

7299379, Nov 20, 2007

Jun 27, 2003

10/607772

Richard L. Coulson - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 12/16

714 20, 714 5, 710260, 710262, 711113, 711112

An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.

2006026, Nov 23, 2006

May 23, 2005

11/135729

Richard Coulson - Portland OR, US

G06F 17/30

707205000

Various embodiments of the invention may write start-up files to contiguous locations in a storage medium before entering a powerdown state. After entering the powerdown state, to start a new operational state the start-up files may be read from the contiguous locations rather than from conventional non-contiguous locations, thus reducing the amount of time required to access those start-up files and reach the operational state.

8291297, Oct 16, 2012

Dec 18, 2008

12/316986

Richard Coulson - Portland OR, US
Albert Fazio - Saratoga CA, US
Jawad Khan - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G11C 29/00

714764, 714765

When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

2006012, Jun 8, 2006

Jan 24, 2006

11/338232

Richard Coulson - Portland OR, US
Brian Leete - Beaverton OR, US

G01K 1/00

702130000

A temperature sensitive memory, such as a ferro-electric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In such case, the system is ready for shutdown without the loss of critical data.

6317875, Nov 13, 2001

Jan 15, 1999

9/231132

Knut S. Grimsrud - Forest Grove OR
Richard L. Coulson - Portland OR

Intel Corporation - Santa Clara CA

G06F 945

717 9

Execution time performance of one or more applications that are dynamically loaded for execution post initial loading is improved by invoking selected parts of the one or more applications for execution post initial loading to allow disk locations accessed and the order the disk locations are accessed to load the selected parts of the one or more applications for execution post initial loading to be traced, and in turn, based at least in part on the order the disk locations are accessed, alternate disk locations to be identified to store the selected parts of the one or more applications to reduce time required to load the selected parts of the one or more applications for execution post initial loading.

6914853, Jul 5, 2005

Nov 12, 2003

10/712432

Richard L. Coulson - Portland OR, US

Intel Corporation - Santa Clara CA

G11C008/00

365236, 365145, 36518511, 36518524, 711103

A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the block is accessed, the counter is incremented, allowing a memory controller to level usage and to rectify any problems associated with wear out of that block. A method for incrementing the counter is also included.

7275135, Sep 25, 2007

Aug 31, 2001

09/945266

Richard L. Coulson - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 12/00

711143, 711160

An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be made based on the usage timeframe information.