DR. RICHARD J. TREVINO, M.D.
Medical Practice at Jackson Ave, San Jose, CA
License number
California C29426
Category
Medical Practice
Type
Otolaryngology
Address
Address
280 N Jackson Ave SUITE C, San Jose, CA 95116
Phone
(408) 926-5300
(408) 926-5395 (Fax)
(408) 926-5395 (Fax)
Personal information
See more information about RICHARD J. TREVINO at radaris.comName
Address
Phone
5227 E Kaviland Ave, Fresno, CA 93725
539 W Remington Dr, Sunnyvale, CA 94087
466 Rainier Dr, Salinas, CA 93906
4707 Kentfield Rd APT 8, Stockton, CA 95207
627 Edan Ave, Stockton, CA 95207
Organization information
See more information about RICHARD J. TREVINO at bizstanding.comRichard J. Trevino, MD
280 N Jackson Ave, San Jose, CA 95116
Industry:
Mfg Surgical Appliances/Supplies
Doing business as:
Sonus-USA
Phone:
(408) 926-5300 (Phone)
Receptionist Secretarys:
Richard J. Trevino (President, Otolaryngology Allergist, Medical Doctor),Cathy Mcgowen (Office Manager),Cindy Brown (Director Of Audiology),...
Richard J Trevino Inc - Richard J Trevino MD
280 N Jackson Ave STE C, San Jose, CA 95116
Categories:
Hearing Aids & Assistive Devices Retail, Otolaryngology Physicians & Surgeons, Physicians & Surgeons
Phone:
(408) 926-5300 (Phone)
RICHARD J. TREVINO, A PROFESSIONAL CORPORATION
280 N Jackson Ave STE C, San Jose, CA 95116
Registration:
Sep 30, 1975
State ID:
C0755101
Business type:
Articles of Incorporation
President:
Richard J. Trevino (President)
Agent:
Richard J. Trevino, M.d,San Jose, CA 95116 (Physical)
Professional information
See more information about RICHARD J. TREVINO at trustoria.com
Richard Jose Trevino, San Jose CA
Richard Jose Trevino, San Jose CA
Specialties:
Otolaryngology, Otolaryngic Allergy
Work:
Physicians Medical Group of San Jose
280 N Jackson Ave, San Jose, CA 95116
280 N Jackson Ave, San Jose, CA 95116
Education:
The University of Texas Southwestern (1964)
High Density Chip Level Package For The Packaging Of Integrated Circuits And Method To Manufacture Same
High Density Chip Level Package For The Packaging Of Integrated Circuits And Method To Manufacture Same
US Patent:
6872589, Mar 29, 2005
Filed:
Feb 6, 2003
Appl. No.:
10/360845
Inventors:
Jan I. Strandberg - San Jose CA, US
Richard Scott Trevino - San Jose CA, US
Thomas B. Blount - San Jose CA, US
Richard Scott Trevino - San Jose CA, US
Thomas B. Blount - San Jose CA, US
Assignee:
Kulicke & Soffa Investments, Inc. - Wilmington DE
International Classification:
H01L021/44, H01L021/48, H01L021/50
US Classification:
438106, 438108
Abstract:
A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region. The thin film interconnect structure comprises (i) a first dielectric layer formed directly on the first surface of the metal substrate and extending over the aperture; (ii) a first metalization layer, formed over the first dielectric layer, comprising a plurality of signal lines positioned over the first region of the thin film interconnect structure and a first plurality of bonding pads positioned over the second region of the thin film interconnect structure; and (iii) a second plurality of bonding pads on the top surface of the thin film interconnect structure. The first plurality of bonding pads have a first pitch appropriate for attaching the integrated circuit die to the package and the second plurality of bonding pads have a pitch greater than the first pitch. Other embodiments of chip level packages as well as various methods for forming such packages are also disclosed.
High Density Chip Level Package For The Packaging Of Integrated Circuits And Method To Manufacture Same
High Density Chip Level Package For The Packaging Of Integrated Circuits And Method To Manufacture Same
US Patent:
6953999, Oct 11, 2005
Filed:
Feb 16, 2005
Appl. No.:
11/059825
Inventors:
Jan I. Strandberg - San Jose CA, US
Richard Scott Trevino - San Jose CA, US
Thomas B. Blount - San Jose CA, US
Richard Scott Trevino - San Jose CA, US
Thomas B. Blount - San Jose CA, US
Assignee:
Kulicke and Soffa Investments, Inc. - Wilmington DE
International Classification:
H01L023/48, H01L023/52, H01L029/40
US Classification:
257778, 257786
Abstract:
A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region. The thin film interconnect structure comprises (i) a first dielectric layer formed directly on the first surface of the metal substrate and extending over the aperture; (ii) a first metalization layer, formed over the first dielectric layer, comprising a plurality of signal lines positioned over the first region of the thin film interconnect structure and a first plurality of bonding pads positioned over the second region of the thin film interconnect structure; and (iii) a second plurality of bonding pads on the top surface of the thin film interconnect structure. The first plurality of bonding pads have a first pitch appropriate for attaching the integrated circuit die to the package and the second plurality of bonding pads have a pitch greater than the first pitch. Other embodiments of chip level packages as well as various methods for forming such packages are also disclosed.
High Density Substrate For The Packaging Of Integrated Circuits
High Density Substrate For The Packaging Of Integrated Circuits
US Patent:
2003019, Oct 23, 2003
Filed:
Apr 23, 2002
Appl. No.:
10/128813
Inventors:
Jan Strandberg - San Jose CA, US
Richard Trevino - San Jose CA, US
Thomas Blount - San Jose CA, US
Richard Trevino - San Jose CA, US
Thomas Blount - San Jose CA, US
Assignee:
Kulicke & Soffa Investments, Inc. - Wilmington DE
International Classification:
H01L023/053, H01L023/12, H01L023/34, H01L023/48, H01L023/52, H01L029/40
US Classification:
257/778000, 257/737000, 257/738000, 257/700000, 257/774000, 257/758000, 257/712000, 257/704000
Abstract:
A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second primary opposed surfaces and an aperture formed therebetween. A flexible thin film interconnect structure having bottom and top opposing surfaces is formed over the first primary surface of the metal substrate and over the aperture such that a first region of the bottom surface is in direct contact with the first surface of the metal substrate and a second region of the bottom surface is opposite the aperture. Within the second region of the bottom surface are a first plurality of exposed bonding pads having a first pitch appropriate for attaching the integrated circuit die to package. The top surface of the flexible thin film interconnect structure includes a second plurality of exposed bonding pads having a pitch greater than the first pitch.