MR. RICHARD HUNTER JOHNSON, RPH
Pharmacy at Kildaire Farm Rd, Cary, NC
License number
North Carolina 6683
Category
Pharmacy
Type
Pharmacist
Address
Address
929 Kildaire Farm Rd, Cary, NC 27511
Phone
(919) 467-0192
(919) 467-9729 (Fax)
(919) 467-9729 (Fax)
Professional information
Quality Test Engineer At Tmng
Location:
Raleigh-Durham, North Carolina Area
Industry:
Information Technology and Services
Work:
TMNG
- Cary, NC May 2011 - Jun 2013
-
Quality Test Engineer
TNMG Global
- Cary, NC Aug 2009 - Jul 2010
-
Quality Test/Network Engineer
Collabera (formerly GCI),
Nov 2005 - Nov 2007
-
UAT Manager BVOIP
AT&T
2005 - 2007
-
BVOIP UAT Manager
Acterna
1999 - 2003
-
Design Verification Engineer
Education:
Pierce College 1975 - 2011
IT, Network Administration and Security
IT, Network Administration and Security
Richard Johnson - Cary, NC
Work:
LGBT Center of Raleigh
VOLUNTEER SECRETARY / GENERAL STAFF Sears
APPLIANCE/MATTRESS SALES CONSULTANT North Carolina State University - Raleigh, NC
VOLUNTEER ITALIAN LANGUAGE TUTOR North Carolina State University - Raleigh, NC
ASSISTANT DIRECTOR FOR THE ITALY SUMMER STUDY
VOLUNTEER SECRETARY / GENERAL STAFF Sears
APPLIANCE/MATTRESS SALES CONSULTANT North Carolina State University - Raleigh, NC
VOLUNTEER ITALIAN LANGUAGE TUTOR North Carolina State University - Raleigh, NC
ASSISTANT DIRECTOR FOR THE ITALY SUMMER STUDY
Education:
NORTH CAROLINA STATE UNIVERSITY - Raleigh, NC
Spanish, Language and Literature UNIVERSIDAD INTERNACIONAL - Cuernavaca, Mor.
Spanish, Language and Literature Studies UNIVERSITA PER STRANIERI - Perugia, Umbria
Italian Studies
Spanish, Language and Literature UNIVERSIDAD INTERNACIONAL - Cuernavaca, Mor.
Spanish, Language and Literature Studies UNIVERSITA PER STRANIERI - Perugia, Umbria
Italian Studies
Skills:
Spanish and Italian Fluency, Educating, Sales, Leadership, Counseling, Merchandising, Study Abroad Experience, Interpersonal Communications, Excellent Computer/Organization Skills
Architecture And Instructions For Accessing Multi-Dimensional Formatted Surface Memory
US Patent:
2011007, Mar 31, 2011
Filed:
Sep 24, 2010
Appl. No.:
12/890171
Inventors:
John R. Nickolls - Los Altos CA, US
Brian Fahs - Los Altos CA, US
Lars Nyland - Carrboro NC, US
John Erik Lindholm - Saratoga CA, US
Richard Craig Johnson - Cary NC, US
Brian Fahs - Los Altos CA, US
Lars Nyland - Carrboro NC, US
John Erik Lindholm - Saratoga CA, US
Richard Craig Johnson - Cary NC, US
International Classification:
G06F 12/00
US Classification:
345564
Abstract:
One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.
Virtual Architecture And Instruction Set For Parallel Thread Computing
US Patent:
8321849, Nov 27, 2012
Filed:
Jan 26, 2007
Appl. No.:
11/627892
Inventors:
John R. Nickolls - Los Altos CA, US
Henry P. Moreton - Woodside CA, US
Lars S. Nyland - Carrboro NC, US
Ian A. Buck - San Jose CA, US
Richard C. Johnson - Cary NC, US
Robert S. Glanville - Cupertino CA, US
Jayant B. Kolhe - Milpitas CA, US
Henry P. Moreton - Woodside CA, US
Lars S. Nyland - Carrboro NC, US
Ian A. Buck - San Jose CA, US
Richard C. Johnson - Cary NC, US
Robert S. Glanville - Cupertino CA, US
Jayant B. Kolhe - Milpitas CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717146
Abstract:
A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e. g. , synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e. g. , data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.
Efficient Predicated Execution For Parallel Processors
US Patent:
2011007, Mar 31, 2011
Filed:
Sep 27, 2010
Appl. No.:
12/891629
Inventors:
Richard Craig Johnson - Cary NC, US
John R. Nickolls - Los Altos CA, US
Robert Steven Glanville - Cupertino CA, US
John R. Nickolls - Los Altos CA, US
Robert Steven Glanville - Cupertino CA, US
International Classification:
G06F 9/30, G06F 9/46
US Classification:
712208, 718107, 712E09023, 712E09028
Abstract:
The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane.
Unanimous Branch Instructions In A Parallel Thread Processor
US Patent:
2011007, Mar 24, 2011
Filed:
Jun 14, 2010
Appl. No.:
12/815226
Inventors:
John R. Nickolls - Los Altos CA, US
Richard Craig Johnson - Cary NC, US
Robert Steven Glanville - Cupertino CA, US
Guillermo Juan Rozas - Los Gatos CA, US
Richard Craig Johnson - Cary NC, US
Robert Steven Glanville - Cupertino CA, US
Guillermo Juan Rozas - Los Gatos CA, US
International Classification:
G06F 9/38
US Classification:
712234, 712E09045
Abstract:
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.
Unanimous Branch Instructions In A Parallel Thread Processor
US Patent:
8615646, Dec 24, 2013
Filed:
Jun 14, 2010
Appl. No.:
12/815201
Inventors:
John R. Nickolls - Los Altos CA, US
Richard Craig Johnson - Cary NC, US
Robert Steven Glanville - Cupertino CA, US
Guillermo Juan Rozas - Los Gatos CA, US
Richard Craig Johnson - Cary NC, US
Robert Steven Glanville - Cupertino CA, US
Guillermo Juan Rozas - Los Gatos CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
G06F 9/32
US Classification:
712234, 712226
Abstract:
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.
Extended-Precision Integer Arithmetic And Logical Instructions
US Patent:
8615541, Dec 24, 2013
Filed:
Sep 23, 2010
Appl. No.:
12/889354
Inventors:
Richard Craig Johnson - Cary NC, US
John R. Nickolls - Los Altos CA, US
John R. Nickolls - Los Altos CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 7/38
US Classification:
708495, 708524
Abstract:
The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.