Richard Henry Lane
Physician at Bannock, Boise, ID

5755831, May 26, 1998

Feb 22, 1995

8/394543

Richard Lane - Boise ID

Micron Communications, Inc. - Boise ID

H01M 218

296231

A method of forming a button-type battery includes, a) providing a conductive first terminal housing member, a conductive second terminal housing member, an anode, and a cathode; b) providing an anode/cathode separator, the separator being pre-configured with a self-aligning shape for self-aligning receipt relative to one of the first or second terminal housing members or the cathode; c) positioning the pre-configured separator relative to the one of the first or second terminal housing members or cathode, the pre-configured separator shape facilitating final alignment of the separator relative to the one of the first or second terminal housing members or the cathode; and d) joining the first and second terminal housing members together into a sealed battery assembly, with the anode, cathode and separator being received within the sealed battery assembly. A button-type battery construction is also disclosed.

6773980, Aug 10, 2004

Dec 30, 2002

10/334382

Brenda D. Kraus - Meridian ID
Richard H. Lane - Boise ID

Micron Technology, Inc. - Boise ID

H01L 218242

438239, 438253, 438396, 438660, 438762

The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

6693014, Feb 17, 2004

Nov 1, 2002

10/285488

Mark Fischer - Boise ID
Charles H. Dennison - Boise ID
Fawad Ahmed - Boise ID
Richard H. Lane - Boise ID
John K. Zahurak - Boise ID
Kunal R. Parekh - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21336

438303, 438549

A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices.

6372574, Apr 16, 2002

Jun 2, 2000

09/586321

Richard H. Lane - Boise ID
Fred Fishburn - Boise ID

Micron Technology, Inc. - Boise ID

H01L 218242

438253, 438244, 438386, 438387, 438396, 438669, 438957

A method of patterning a metal layer includes masking a first portion of a metal layer while leaving a second portion of the metal layer unmasked over a substrate. With the masking in place, the second portion is reacted with silicon to form a metal silicide from the metal layer. The metal silicide is removed from the substrate while substantially leaving the first portion on the substrate. The masking is removed from the substrate. A method of patterning a metal layer includes depositing and patterning a silicon comprising layer over a substrate. A metal layer is formed over the patterned silicon comprising layer, and includes a portion extending to elevationally inward of the metal layer. Metal of the metal layer is reacted with silicon of the silicon layer to form a metal silicide and leave at least some of the portion unreacted. The metal silicide is removed from the substrate while substantially leaving the unreacted portion of the metal layer on the substrate.

6414364, Jul 2, 2002

Jul 24, 2001

09/911580

Richard Lane - Boise ID
Randhir Thakur - San Jose CA

Micron Technology, Inc. - Boise ID

H01L 2976

257397, 257510, 428424, 428435

A novel shallow-trench isolation (STI) structure and process for forming it is described. More particularly, a recess is formed in a semiconductor substrate. An oxide layer is formed in the recess using thermal oxidation or high-pressure oxidation. If the oxide layer is formed by high-pressure oxidation, then a nitrogen containing gas may be flowed into a high-pressure oxidation chamber to add nitrogen to the oxide layer. The recess may then be filled with a dielectric layer by a deposition process. Alternately, the dielectric layer may be formed using high-pressure oxidation.

6261899, Jul 17, 2001

May 29, 1998

9/087114

Richard H. Lane - Boise ID
John K. Zahurak - Boise ID

Micron Technology, Inc. - Boise ID

H01L 218242

438253

In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

2002008, Jul 11, 2002

Feb 8, 2002

10/071456

David Dickerson - Boise ID, US
Richard Lane - Boise ID, US
Charles Dennison - Meridian ID, US
Kunal Parekh - Boise ID, US
Mark Fischer - Boise ID, US
John Zahurak - Boise ID, US

H01L029/00, H01L021/76

257/510000

In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.

6080655, Jun 27, 2000

Aug 21, 1997

8/917666

John H. Givens - Meridian ID
Richard H. Lane - Boise ID

Micron Technology, Inc. - Boise ID

H01L 214763

438626

A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers. The void may be etched in a two part process in which a non-selective etchant etches through the third dielectric layer to an intermediate level in the second dielectric layer, and then a selective etchant etches through the remaining portion of the second dielectric layer to the first dielectric layer. The third dielectric layer is subsequently covered with a conductive material, and the void is filled with a portion of the conductive layer.

7273778, Sep 25, 2007

Feb 8, 2005

11/053781

Dale W. Collins - Boise ID, US
Richard H. Lane - Boise ID, US
Rita J. Klein - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/8242

438239, 438243, 438253, 438254, 438255, 438393, 438396, 438397, 438398, 257E21011, 257E21019

The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.

6979849, Dec 27, 2005

Dec 31, 2003

10/750737

Richard Lane - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L027/108, H01L029/76, H01L029/94, H01L031/119

257296, 257297, 257298, 257300, 257306, 257311, 257906

A memory cell having improved interconnect. Specifically, a dynamic random access memory (DRAM) based content addressable (CAM) memory cell is provided. The lower cell plate of the storage capacitor is implemented to provide an interconnect for the access transistor and the CAM portion of the memory cell. Conductive plugs are coupled to each of the transistors and coupled directly to the lower cell plate of the capacitor.