Richard Givens Smith
Nursing at Tarragon Ln, Fort Collins, CO

2009024, Sep 24, 2009

Mar 24, 2008

12/054317

Richard W. Smith - Fort Collins CO, US
Hang Kwan - San Bruno CA, US
Manzurul Khan - San Jose CA, US

G06F 17/50

716 6

A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.

2009025, Oct 15, 2009

Apr 10, 2008

12/100505

Richard W. Smith - Fort Collins CO, US

G06F 17/50

716 6

A design tool for automatically identifying minimum timing violation corrections in an integrated circuit (IC) design includes program instructions executable by a processor to identify locations to add a delay along each circuit path having a minimum timing violation. The tool may also sequentially try each of a plurality of circuit changes that add the delay and to evaluate a result of each circuit change until an acceptable percentage of the minimum timing violation has been corrected. In response to each circuit change, the design tool may update an internal node report, which includes a listing of circuit nodes and a maximum timing slack available at each node, by reducing a maximum slack value of each affected node by an amount of the added delay. The design tool may generate an output report that includes a listing of the circuit changes which correct the minimum timing violations.

2009022, Sep 3, 2009

Feb 29, 2008

12/039833

Richard W. Smith - Fort Collins CO, US

G06F 17/50

716 6

A design tool for reducing half-cycle common path pessimism includes program instructions storable on a computer readable medium. The program instructions may be executable by a processor to receive a timing report for the IC. For each source clock path and destination clock path of each half-cycle timing path, the design tool may identify common circuit elements, and determine a process, voltage, and temperature (PVT) path delay value corresponding to PVT scaling of each identified common circuit element. The design tool may sum together the PVT path delay values of each identified common circuit element to obtain a total PVT compensation value. The design tool may also generate a new total skew value by subtracting the total PVT compensation value from a total compensated skew value, and generate a corrected timing report that includes the new total skew values.