Richard E Davis, JR
Electrician at Holland, Littleton, CO
License number
Colorado 910555
Issued Date
Sep 11, 1991
Renew Date
Apr 5, 1995
Type
Electrical Apprentice
Address
Address
5172 S Holland St S. HOLLAND, Littleton, CO 80123
Personal information
See more information about Richard E Davis at radaris.comName
Address
Phone
5051 Upton Ct, Denver, CO 80239
5056 S Mabre Ct, Littleton, CO 80123
Professional information
Parallel Frame Synchronizer For Detecting Forward-Ordered/Reverse-Ordered, Inverted/Non-Inverted Data
US Patent:
5592518, Jan 7, 1997
Filed:
Mar 28, 1994
Appl. No.:
8/219695
Inventors:
Richard M. Davis - Littleton CO
Thad J. Genrich - Aurora CO
Mark W. Hall - Franktown CO
Thad J. Genrich - Aurora CO
Mark W. Hall - Franktown CO
Assignee:
Hughes Electronics - Los Angeles CA
International Classification:
H04L 700
US Classification:
375368
Abstract:
A high speed parallel frame synchronizer provides high speed frame synchronization functions utilizing parallel processing techniques implemented with commercially available components. Serial input data is demultiplexed to an N bit wide word at a rate of 1/N of the input clock frequency. A total of N parallel correlators are used to detect the frame synchronization pattern. Outputs of the correlators are arbitrated using a priority encoder which provides synchronization information to the frame synchronizer. One embodiment of this invention utilizes 4N correlators to simultaneously provide for synchronization of true/inverted and forward/reverse data generated by real-time or playback data sources.
Parallel Cascaded Integrator-Comb Filter
US Patent:
5596609, Jan 21, 1997
Filed:
Jun 25, 1996
Appl. No.:
8/670109
Inventors:
Thad J. Genrich - Aurora CO
Richard M. Davis - Littleton CO
Bruno A. Martinez - Denver CO
Richard M. Davis - Littleton CO
Bruno A. Martinez - Denver CO
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H04B 110
US Classification:
375350
Abstract:
A high speed digital filter for use in digital interpolation and decimation provides a parallel processing implementation for integrator stages of a cascaded integrator-comb (CIC) filter. The parallel structure of the present invention is easily cascadeable since it allows subsequent integrator stages access to intermediate samples generated by preceding integrator stages. The parallel integrator structure may be implemented directly or may be reduced in complexity by removing redundant logic for use in decimator output sections or interpolator input sections. The parallel implementation of a CIC filter allows much higher sample rate filtering to be implemented with fewer standard CMOS logic devices than currently recognized implementations.